Hello,

after about one year I found the time to work on MOUSE again. The breadboard version still works, but trying to get a version on a prototype board failed. So I decided to build a "real" pcb for it.
If somebody got quick check the current schematics would help to correct things before I go into the "routing nightmare"

Mario.

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How should I know what I think, until I hear what I've said.

I am far from a 6502 expert, but some comments:

What clock frequency are you using? I see you are using the 6850 without a baud rate generator so that will limit your option quite considerably.

A button for NMI will allow you to experiment with that facility for almost no board space.

Likewise a line for IRQ from the UART would be a nice simple "risk free" addition and allow you to experiment with interrupt driven serial.

You are tying CSs and OEs together. I'm sure this works on many devices, but is it necessary? Eg. the datasheet for the Atmel 28C256 says write mode requires OE to be high.

If it was me I would probably want another output device, like a simple latch with some LEDs.

Good luck.

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8 bit fun and games: https://www.aslak.net/

Hey, welcome back. There's nothing I see at first glance, but that would be me . What happened with the prototype board? Sounds worrying ...

A couple of notes:

1. I see you are deriving your Ø2 signal from PHI2out of the 65C02. This is not a recommended procedure, per the WDC data sheet. PHI1out and PHI2out should remain unused and anything that needs the MPU clock should get that signal directly from the clock oscillator.
   
   PHI1out and PHI2out exist only for use in applications in which an NMOS 6502 is being replaced by the 65C02. Both signals lag PHI2 (in) by an unspecified amount, which may in some cases cause timing problems if used to clock other devices.
   
   
2. Excepting the MC6850, your hardware is CMOS. Hence you should be using 74AC or 74HC glue logic, not 74LS. 74AC is the preferred choice if performance matters, but requires some attention to construction methods to avoid excessive ringing. In particular, the 78xx139 decoder is a relatively slow device, so is a good place for the 74AC logic.
   
   
3. Speaking of the 6850, that would be my second to last choice for a UART. It has no on-board baud rate generator and no hardware reset function. Also, its timing specs will significantly limit your system's maximum speed. This device is quite primitive, even by the standards of the 1970s. Much better UARTs are available.
   
   
4. I don't see any circuitry for converting between TIA-232 and TTL voltage levels. What are you planning to connect to your UART?
   
   
5. You are using Ø2 to gate chip selects, which is not recommended practice. Chip selects should be gated only by address decoding, as the goal is to have the selected device ready for access as soon as possible when Ø2 goes high. As you have it configured, that will not happen.
   
   
6. Your R/W signal should be the 65C02's RWB output gated by Ø2. The data bus is not valid when Ø2 is low, which can in some cases give rise to obdurate problems if not accounted for in the design. Succinctly stated, you should not write-enable a device when Ø2 is low. This rule does not apply to an 65xx I/O hardware, such as the 65C22.
   
   
7. As Aslak3 suggested, a push button on /NMI would be useful. You can debounce it with a DS1813, as you did with your reset circuit.
   
   
8. Also, as suggested, /IRQ should be attached to your UART for later development purposes. IRQ-driven I/O is much more efficient than polled, especially when writing to the output device (terminal, etc.).

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Hello everyone,

thanks for the feedback. The clock will be an 1.8432 MHz oscillator what gives me a proper speed for the CPU and 28.800 baud or 115.200 for the ACIA.
Using PHI2 in the address decoding instead of using it on the R/W line is part of Garth's Primer (http://wilsonminesco.com/6502primer/addr_decoding.html) and works quite well on my breadboard.
The ACIA will drive a Serial2USB converter, that also provides 5V to the circuit, so I need no level converter for the serial line. The 6850 has no external reset, it has some kind of soft-reset by writing 11 to the counter divide select bits.
Both interrupt lines already have a label so I can connect them easily to additional parts of the circuit. Maybe its a good idea to add the /IRQ line to the ACIA.
Using the clock signal directly instead of using PHI2 sounds reasonable and should make the routing a bit easier, because I can move the clock source around the board. I'll use 74HC devices, even if the schematic says that there are LS devices. There are no special parts in KiCad for AC or HC, but I can simply change the "value" of the part. The footprints are the same, so it's only a matter of naming the parts.
The ROM should not be written, so I can simply tie together /CE and /OE for ROM and RAM.

The new version of the schematic respects PHI2 (or CLOCK) for READ / WRITE Operations but makes logic more complex. I'm not sure right now if I should use this or the simple version for the pcb.

Mario.

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How should I know what I think, until I hear what I've said.

It would be good to pull SO\ high, through a resistor. With most brands of 65c02, letting it float would be an absolute no-no. WDC's supposedly has a (very weak) internal pull-up, but I'm not sure it should be relied upon. I might have more confidence in it if I had one installed and easy to check by putting various values of resistors from there to ground to see if it can handle a light load trying to pull to ground and still remain high.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

How about using the other half of the '139 to develop the Φ2 qualified Read/Write signals? If you think you might want to program the EEPROM in-circuit at some time, could a PCB jumper connecting the EEPROM /WE line to either VCC or the Φ2 qualified Write signal provide an EEPROM "write protect" or "write enable" mechanism?

While the circuit below decodes a single 16K block for I/O (while doubling your ROM space), which may seem limiting, remember that you can use the active high chip select in addition to the active low chip select on 65xx peripheral devices and your 6850 device to decode unique blocks within that I/O space ($8010-$801F, $8020-$802F, $8040-$804F, $8080-$808F, $8100-$810F, etc.) as described in Garth's Primer.

Good luck with your project, Sir.

Cheerful regards, Mike

The second approach is far better. I don't see why it is more complex. On the other hand may I suggest another solution



This gives you a 16 ROM range and 8 2k IO Ranges with the same number of ICs and the same footprint on the PCB. You can combine this with the write-protect jumper for the EEPROM as Michael has suggested. And you should add the suggestions from BDD, that is add a pull-up to SO and not use PHI2O from the W65C02 but instead use the CLOCK as a substitute. Use CMOS parts if possible.

Cheers, Peter

Hello,

thanks for all the suggestions, but there's no need for a different address logic at the moment. I have two different versions of Daryls decoder GAL that I can use. But this is a minimal board to get my breadboard version that works well since a year to a pcb. With the experience I get from making the simple board I'll start to make a more complex version, using a GAL for address decoding. For now I'm happy if the second version of the circuit is ok, even with the simple logic.

Mario.

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How should I know what I think, until I hear what I've said.

I added an additional expansion header and a header for a simple 128x64 LCD display. The routing is done and the order for the pcb is placed. This is by far the most complex pcb I've done.
It's presumably anything but perfect, but I hope it will do it's job. Learning KiCad was one side effect of this.

_________________
How should I know what I think, until I hear what I've said.

You don't want all those filled planes (aka ground pours) that I see in the illustration. Be sure to read the topic on PCB design considerations if you already haven't done so.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

At 1.8 MHz, I wouldn't worry about the tiny effects of ground pours.

The PCB arrived today, maybe I'll find the time to solder the thing in the next days.

_________________
How should I know what I think, until I hear what I've said.