65816 Hardware Memory Protection

[kc5tja]

First of all, let me begin by stating that the ABORTB pin supports single- and multi-address-space MMU designs. There is no set pretext, unlike in-chip MMUs of other processors.

Quote:

Nope. IIRC, the x86 supports multiple page sizes from 1k to about 32k or so, and there's a special 4m mode for I/O.

No. The x86 architecture supports only truely 4KiB and 4MiB pages. There are no portable provisions for anything else. Some models also support a 2MiB page size, but this is not yet (will ever be?) universally supported by future generations of CPUs.

There are no page sizes smaller than 4KiB for x86 CPUs.

[TMorita]

kc5tja wrote:

First of all, let me begin by stating that the ABORTB pin supports single- and multi-address-space MMU designs. There is no set pretext, unlike in-chip MMUs of other processors.

Quote:

Nope. IIRC, the x86 supports multiple page sizes from 1k to about 32k or so, and there's a special 4m mode for I/O.

No. The x86 architecture supports only truely 4KiB and 4MiB pages. There are no portable provisions for anything else. Some models also support a 2MiB page size, but this is not yet (will ever be?) universally supported by future generations of CPUs.

There are no page sizes smaller than 4KiB for x86 CPUs.

Looks like you're right. I just checked the manuals.

I must be thinking of the 68030 MMU.

Toshi