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Shift to the left,
Shift to the right,
Mask in, Mask Out,
BYTE! BYTE! BYTE!

I have a related question which maybe fits this thread. It came up while coding my Crude Emulator for the 65816: When a RESET is triggered, p. 201 of Eyes and Lichty says that the MSB of the Stack Pointer is set to $01. It says nothing about the LSB. Do we know if it is preserved or is the state undefined afterwards?

At power-up, the LSB of SP is random. Otherwise, I don't know what its state might be. I could burn an EPROM for POC that writes SP to an otherwise unused location in RAM at reset and see what pops up.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I don't know why I didn't think to address this the first time around (three years ago), although BDD alluded to it WRT the '816. When parameters are passed to a subroutine on the hardware stack, it is common for the subroutine to access them by doing for example,

to reach past the subroutine return address and past two more bytes, to the parameter byte just past that. It could easily be more, like 108,X. In that case, you can see that you would want the stack initialized to $FF; because if it were to ever wrap (like if you started with S=03 instead of $FF, this indexing could get you out of the stack area and into page 2. [Edit: This is mentioned in the note in the middle of chapter 5 of my 6502 stacks treatise which has 19 chapters plus appendices. There's more explanation there.]

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

The state of the LSB of S is undefined after power-up -- just garbage. But reset is a different matter -- is that really what you intended to ask? (Reset and power-up aren't the same. The chip can be reset repeatedly after it's powered up.)

Reset takes whatever is already in the LSB -- power-up garbage or otherwise -- and decrements it by three. That's because reset is a form of interrupt, and involves pushing via the stack pointer (although dummy cycles replace the writes if the interrupt is a reset). Table 5-7, row 22a of the '816 data sheet shows this.

[Edit:] Section 2.5 says, "When Reset is brought high, an interrupt sequence is initiated." Apparently the reset interrupt is edge-triggered (like NMI, just with opposite polarity). Multiple iterations of the reset interrupt sequence will not occur, contrary to some speculation I expressed earlier.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Right. I know it's garbage after power-up, but had never thought about RESET until I had to write a routine for it ... thanks for the explanation!