We know that the RTI instruction has a fixed instruction time (6 cycles). But what I have never seen is exactly at what point are interrupts actually allowed during the course of that instruction. Is it at instruction clock 1,2,3,4,5, or only after the conclusion of cycle 6?

Anyone know?

I can't speak for the exact timing of the 65C02, but I can tell you that the 65C816 pulls the status register at cycle 4, which would enable interrupts if the I bit in the stack copy of SR is clear. However, you should note that the MPU doesn't actually acknowledge an IRQ until the completion of the current instruction. Hence the exact point at which interrupts are enabled in the RTI instruction sequence isn't particularly important.

Incidentally, in 65C816 native mode, RTI requires seven clock cycles.

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Thanks. I was thinking as well as the 6502 would not check the flags until after the RTI instruction has finished.

You can run experiments fairly readily with visual6502 by using specific URLs to set up your test code and fire an interrupt at a specific time. See for example
viewtopic.php?p=23519#p23519
and see the URL section in the help page of the simulator.

When I was looking into getting the 6502 emulation right for jsbeeb, I think my conclusion was that RTI pulls the flags off the stack before the moment that pending IRQs are checked. So it should be possible for an interrupt to be serviced immedately after the RTI and prior to the instruction it returns to. This is also stated here: