Yes indeed lol.

BTW do you think I need pull up resistors on the input side of the buffers? The AVR has this on anyway, but I was thinking of erratic behaviour from the buffers themsevles if that part of the bus input is high impendance. What do you think?

No I don't think it is necessary, in any case there is almost always someone active on the bus. I never used pull-ups in my projects.

Cool. I ended up putting 10K pullups on the signals buffer IC as those (the incoming signals /ROM select, /RAM select, etc.) are active-low. The rest have been left as-is.

Here's an updated firmware source file (now optimised) - see attached.

I've uploaded a video of both the GAL bus monitor and the AVR one. Each is demo'd attahed to my first 6502 home brew computer running at a glorious 1Hz ( ) so that you can see what's going on.

GAL:
https://www.youtube.com/watch?v=2EZGFIB9Wv4

AVR:
https://www.youtube.com/watch?v=wDRIcP--S74

I have to say the AVR one looks like it could be much more informative! But both are great things to have built and finished. Finishing seems to be the hardest part.

I totally agree. One of the main reasons for creating these is to help diag my newer 6502 projects as I find converting the buses to hex one cycle at a time is just too onerous and had effictively put me off going further as I've had to do this once already.

Found a random boot issue where the monitor would be unable to boot and a large amount of current being drawn. I suspected that this was down to the buffers sat between the 6502 bus and the AVR having their /enable (G) pins on high impedance in the second or so that the AVR finishes powering/booting. To resolve the issue I've added 10K bus type network pull up resistors on those lines which means, by default, the buffers ICs isolate each side from the other. Seems to have worked thus far.
Here's a new circuit diagram (in case anyone is still awake at the back ):