leeeeee wrote:
Quote:
my only problem is that I couldent find the GAL chip that was in the schematic
It can easily be replaced by an equivalent device, basically any 16x8 or bigger device, or by discrete logic, the equations file for the GAL gives all the logic involved.
A couple of 74LS138s could do most of the work.
Lee.
I've been thinking about this just recently. Here's what I
came up with. Maybe some one would like to check me.
Here's the picture:
Code:
____ ___ ___ ___ ___ ___
CLK \_____/ \_____/ \_____/ \_____/ \_____/ \
_ ______________________
R/W \____________________________
_ __ _________ _________
A0 \_________/ \_________/ \________
_____ _ ________________________________________
RLE \_____/_/
_____ __________________________________________
IOR,RHC \_____/
_______________ _ ______________________________
RHE \_____/_/
_________________________ ______________________
WLC \_____/
___________________________________ _ __________
WLE \_____/_/
___________________________________ _ __________
WHE \_____/_/
___________________________________ ____________
IOW \_____/
_____
R/W ---+----|A Y0|
A0 ---)-+--|B Y1|
| | |C Y2|
| | | Y3|
| | | Y4|--WLC
IO -+-)-)--|/G Y5|--IOR,RHC
CLK -)-)-)--|/G Y6|--IOW
| | | |G Y7|
| | | |_____|
| | |
| | | _____
| +-)--|A Y0|
| +--|B Y1|--RLE
| | Y2|--WLE,WHE
+------|G Y3|--RHE
| |_____|
|
| _____
A4 -)------|A Y0|
| |B Y1|
| | Y2|--CS0
+------|G Y3|--CS1
|_____|
Here's the thousand words
The idea is to multiplex 8 data lines to 16 data lines with
the 16 word aligned on the 8 bit side, that is when address
line 0, ie A0, is 0 we'll read/write the lower 8 of 16 and
when A0 is 1 we'll be reading/writing the high 8 of 16
We'll write the low byte to a register and then write the
high byte directly to the high 8 data lines of the 16
through a tristate buffer while the register drives the
lower 8 data lines of the 16.
For reading we'll read the lower 8 of 16 data lines directly
through a tristate buffer while simultaneously clocking
the high 8 data lines into a register and then we'll read
the high 8 from the register.
So when we read a byte from an address with A0=0 we'll do
a read of the 16 data lines but not when we read with A0=1
When we write to an address with A0=1 we'll do a write of
the 16 data lines but not when we write with A0=0
So we can read/write the 16 bit words a byte at a time in
ascending sequence, little endian style
The basic synchronous bus philosophy is to strobe stuff
on to the bus then provide a clock edge in the midst of the
strobe to clock it in to where ever it's going.
It might be possible to make clocks double as stobes or strobes
double as clocks, but I think that's sloppy, so we need two
decoders, one for strobes and one for clocks.
Four possibilities: write lo, write hi, read lo, read hi
For writing lo, with R/W=0 and A0=0, we need a clock for the
write register, WLC
For writing hi, with R/W=0 and A0=1, we need an enable for the
buffer to strobe the hi byte onto the hi 8 of 16, call it WHE
We also need to enable the previously written write register,
ie strobe the lo byte on to the lo 8 of 16, call it WLE and
since WHE and WLE are always simultaneousm, ie they both occur
iff R/W=0 and A0=1 they can be the same signal.
For reading lo, with R/W=1 and A0=0, we need a strobe to strobe
the lo 8 of 16 on to the 8 bit side, call that RLE and a clock
to clock the hi 8 of 16 in to the read register. Call that RHC
For reading hi, with R/W=1 and A0=1, we need to strobe the
read register on to the 8 bit bus, call that RHE
We also need strobes and clock(s) for the 16 bit reads and
writes.
IDE has two strobes CS0 and CS1 depending on the state of A4
and seperate clocks for reading, IOR, and writing, IOW,
IOR occurs simultaneous with RHC so they can be the same signal.
So we need five strobes
three for the eight bit stuff: WHE-WLE, RLE, RHE
and two for the 16 bit stuff: CS1, CS0
And we need three clocks: WLC, RHC-IOR, IOW
We'll assume an over all strobe/enable/select (whatever you like)
for the multiplexer which I'll call IO and a (the) clock
for timing.
For the 8 bit strobes we need to know if were reading or writing
and are we reading or writing an odd or an even location
and we'll enable them only while IO is active so we need to
decode R/W, A0, and IO, and IO is a gate/enable
2 inputs to decode and a gate for the decoder, so half of a
74139 will work
Same for the 8 bit clocks so we'll decoded from R/W, A0 and gate
with IO but we'll also gate them with the clock
2 inputs and two gates/enables so a 74138 for that
CS1 and CS2 just split the IDE address according to A4 so we just
need A4 and IO for them
2 inputs so there's the other half of the 74139
For the IDE clocks, IOW occurs iff we're writing a hi byte and
IOR iff we're reading a lo byte
so the same 4 inputs as the 8 bit clocks, so we can take them
from the same 74138
And I'd tie the unused inputs high on the (possibly spurious)
theory that it's better to source 40uA than sink 1.6mA
I don't know IDE. The thing I particularly wonder about is:
is there any harm in, or reason not to select CS0 or CS1 when
you're not either reading or writing to the IDE?
If there is, I guess I'll use the other half of 74139 for
something else and decode CS0 and CS1 from RLE, WHE and A4
like so:
Code:
___
RLE----| \ ___
| |O-+-----| \
WHE----|___/ | | |O--CS1
| +--|___/
| |
A4 --+---------)--+
| | ___
| ___ +-----| \
+--| \ | |O--CS0
| | |O------|___/
+--|___/
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