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PostPosted: Sat Jul 25, 2015 3:41 pm 
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Joined: Fri Jul 17, 2015 5:11 pm
Posts: 1
hello,

I am trying to find a way to bootstrap a ROM image (AVR to control a 6502)

The 6502 system is a Oric 1\ Atmos, so i cannot clock the 6502 from the AVR

I am aware you can use a AVR to address the 6502 then release the 6502 reset line, but you have to use 16 address lines and 8 data lines (24 pins for IO)

The interface is a AVR and a SRAM (not using Oric 1 Atmos shadow ram due to difficulty in the timing required for the map signal )

Is there away this can be done by minimizing the IO count

regards

john davis


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PostPosted: Sat Jul 25, 2015 4:18 pm 
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Joined: Mon Jul 20, 2015 6:34 pm
Posts: 62
To reduce pin count you can use serial in parallel out shift registers or counters (limited to sequential access) But you need to tristate the address and databus. I think it's a lot overhead,

How about connecting only through S.O., IRQ and NMI pins? Along with RESET and READY lines you only need 5 I/O pins on the micro. You can use below code to feed 256 bytes of similar bootloader into zero page. It's a bit slow (2-3k per second) but it works. This one is space optimized version. To transfer 1 you trigger IRQ line low for 10 micro seconds and wait for 6502 to handle interrupt >35 microseconds (interrupt code takes 35 cycles but it's better to be on the safe side) You do the same for transferring 0s but using NMI line. You flag the end of transfer by pulling low for at least 3 cycles of 6502 and then pulling high again.

Code:
BOOTLOADER = $00


   *=$FFD5
RESETROUTINE
   SEI
   CLD
   LDX #$FF
   TXS
   LDA #$00   ; Clear everything
   TAY      ; Init index   
   LDX #$08   ; Init bit counting
   CLI
   CLV
   
WAITBOOTLOADER
   BVC WAITBOOTLOADER
   
   JMP $0000

; NMI ROUTINE
; It does the transfer of 0 bits.
; A, X and Y is freely used and not pushed into the stack
; Since foreground task doesn't use any of them and just
; idly wait for the overflow flag from controlling micro.

NMIROUTINE
   SEI
   CLC   
   BCC COMMONPART
   
; IRQ Routine
; It does the transfer of 1 bits.
; A, X and Y is freely used and not pushed into the stack
; Since foreground task doesn't use any of them and just
; idly wait for the overflow flag from micro.
; Also these registers are shared with the NMI routine since
; they are used for same purposes.
; And the routine is exactly same with the NMI routine except
; it sets carry before rotating current byte instead of clearing.
IRQROUTINE      
   SEI
   SEC         
COMMONPART:   
   ROL   
   DEX      
   BNE FINISH    ; 1 bit (0) transferred in, exit.
   LDX #$08   
   STA BOOTLOADER, Y   ; Finish one byte of transfer
   LDA #$00
   INY      
FINISH
   CLI
   RTI      

      
      
   .ORG $FFFA
   
   .DW NMIROUTINE
   .DW RESETROUTINE
   .DW IRQROUTINE
   
   


Sample arduino code,

Code:
void SignalContinue() {
    digitalWrite(SO, LOW); //We should wait at least 3 6502 cycles
    delayMicroseconds(5);
    digitalWrite(SO, HIGH);
    delayMicroseconds(100);
}

void TransmitByteFast(unsigned char val) {
    unsigned char mask = 0x80;
    for (int i = 0; i<8; i++) {
        if (val & mask) {
            //Transmit 1
            digitalWrite(IRQ, LOW);
            delayMicroseconds(10); //Wait 10 micro seconds for interrupt to trigger (approx. 10 cycles)
            digitalWrite(IRQ, HIGH);
            delayMicroseconds(50);  //Wait 60 micro seconds for interrupt to finish it's job (approx. 60 cycles)

        } else {
            //Transmit 0
            digitalWrite(NMI, LOW);
            delayMicroseconds(10); //Wait 10 micro seconds for interrupt to trigger (approx. 10 cycles)
            digitalWrite(NMI, HIGH);
            delayMicroseconds(50);  //Wait 60 micro seconds for interrupt to finish it's job (approx. 60 cycles)

        }
        mask = mask>>1;
    }

}



In the original loader I think you can speed optimize the irq/nmi routines to simply these below and do the byte collecting in the foreground code by employing S.O. flag from micro.

Code:
NMIROUTINE
   ROL
   SEC
   RTI
         
IRQROUTINE
   ASL
   SEC
   RTI


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PostPosted: Sat Jul 25, 2015 7:11 pm 
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Posts: 679
You could reduce the I/O pin count to 16 if you multiplex & latch A0-A7 so that the same pins can be reused for D0-D7.

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AcheronVM: A Reconfigurable 16-bit Virtual CPU for the 6502 Microprocessor


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PostPosted: Sat Jul 25, 2015 8:52 pm 
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Joined: Sun Oct 13, 2013 2:58 pm
Posts: 491
Location: Switzerland
You could try the approach of my IML bootstrap. [url][http://forum.6502.org/viewtopic.php?f=4&t=3374/url] The Oric has a 12MHz base clock that could be used as the AVR clock. Then you need to sync the instruction timing of the AVR to PHI2 that is output from the HSC10017 once you know this you can reset the 6502 and then just feed the bytes that would come normally from a ROM. The only issue will be that you need to count every cycle of your AVR program. Inother words you must use assembler. With this you could fill a RAM that replaces the normal Oric ROMs. Of course you need some decoding logic as well. I only control PHI2 to be able to switch to a faster clock after the ROM image has been loaded.


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PostPosted: Thu Jul 30, 2015 6:29 am 
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Joined: Thu Jun 23, 2011 2:12 am
Posts: 229
Location: Rancho Cucamonga, California
jdavis6809 wrote:
hello,

I am trying to find a way to bootstrap a ROM image (AVR to control a 6502)

The 6502 system is a Oric 1\ Atmos, so i cannot clock the 6502 from the AVR


I don't know if it helps, but I did something similar with my KimStar project: I connected a Propeller to the address bus, data bus, R/W and PHI2 of the MicroKim to work around a defective EPROM.

See https://hackaday.io/project/4418

===Jac


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