First of all, this is my first post. This forum was a valuable asset to me while I did my project. A special thanks to Garth Wilson for his 6502 primer. It was invaluable.
I'm trying to make a prototype for my 6502 project, a psid player.
Here you can see in action,
https://www.youtube.com/watch?v=MBIUJIpaeXwSince I lack the skills in the pcb design compartment I decided to build the prototype apartment style making everything adapt to 6502's 40 pin interface.
My cpu board contains,
- 1 mhz oscillator
- 32kx2 SRAM
- 27C512 EPROM (I only need 1 page of read only memory actually but couldn't find smaller eprom, will be replaced by eeprom)
- Address decoder with bunch of 74 series chips.
And I have a controlling Mcu, it was previously a 8 bit pic. Now it's an arduino uno. It drives the display & sd card and boots 6502 filling required program into it using S.O. / IRQ and NMI pins. Currently it can fill the memory asynchronously 1.5k per second or so, with optimizations it's possible to increase this to 4-5k or so. Arduino is not connected to databus or address bus hence the read only memory requirement.
Boards I've build could be seen in the attached picture. Of course it didn't work in the first time. So I started testing each layer individually. Cpu board tested ok and passed the NOP test. Eprom fitted and it seems to be working ok too. Now to test the sram I thought it would be nice attach a simple circuit to the existing lot so that I can transfer data to arduino. I have a VIA but at this stage of building the circuit it wouldn't be wise to build something around it and introduce more issues. Instead I thought I could fit a 74165 (74HC165 in my case) parallel input serial output shift register as a memory mapped I/O device.
The idea is, decode address for 74165 in a certain memory range. The byte to be sent is addressed as say,
Code:
LDA BYTETOSEND
STA DECODEDADDRESS
; Idle loop enough for arduino to do it's job (serially read data)
Chip select signal for the decoding is tied to the LATCH/ input, data bus is tied to the 8 parallel inputs of the 74165. 6502 code waits a bit after addressing the decoded address so arduino can fetch the data serially. Arduino drives the CLOCK input of 74165 by the way and retrieves data through serial output of 74165 and sends this data serially to the pc. (same CS signal for 74165 is also used as an interrupt signal for arduino )
To keep it simple I now decode full 0-7FFF range to 74165 using NOT A15. Decoding ROM as A15. Accessing the 74165 at $1000. Getting it run I can trace individual bytes indeed sent to the arduino side but they all come as $FFs. (Edit, it's other way around actually... A15 -> 74165, NOT A15 -> ROM. Don't know how to strikethrough written text. )
Well the question is,
1. Feasibility aside, could 74165 indeed be interfaced to 6502 in this fashion?
2. What do you think is wrong with my setup?
I tested these too,
1. Using PHI2 NAND (NOT A15) to decode 74165. This somewhat produces a 1mhz square wave even though my program only accesses $1000 address 11 times and everything else is between $FF00 and $FFFF.
2. I tried to feed low A0-A7 bits into the 74165. I changed the code so that whatever I want to send is addressed between $1000 and $10FF. Still got all $FFs.
ps1: I don't have filtering caps on the VCC line of each IC in this prototype. I know I should add them as soon as possible.
ps2: I fitted SRAMs one on the top of other. Either I'll upgrade in this prototype setup to more capacity sram or place them side by side since they take vertical space and not very usable currently. And I must admit, using sockets for ICs in this setup is not a good idea too. They also take vertical space.