I'm still wondering if it's the presence of TTL inputs which will drag down outputs, and so in a design without TTL inputs, the output levels will be higher than the minimum spec - and therefore within range of a weirdo spec.

I checked the r/W line, too, so I know that I have seen mostly reads. Not really sure from where, though.



I'll take that as my homework for today.

Sounds good. Btw, a reminder: if you're using an analog scope (not a DSO) and you're trying to scope something very specific -- in this case reads from the NMOS SRAM and from that TMS9929 -- it's very helpful to write a tiny loop that repeatedly performs the action you're trying to observe.

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Okay,

I am late with my homework.
I wrote a small program that reads the TMS9929's status register in a tight loop. What we see on the screenshot is the TMS9929's /CSR-pin (blue curve) and the D2-line (yellow curve).
As we can see, the signal level when driven by that NMOS 9929 is just slighty above 4V, so apparently WDC safe.
Using a 3.3k pullup resistor will pull up the level a bit (go figure..) but seems to pull up some noise, too.

OK, so in red I drew the Phase2 waveform in what I suppose to be the the correct relation, and I put the images in a two-frame animation, ie, with and without the pullup (below). It's no surprise to see that the pullup resistor has a distinct effect when Phase2 is low (for example in the first part of cycle 1, which I circled). This is entirely harmless. The 'C02 will always tri-state the data bus during Phase2 low, and ideally (but depending on its wiring) the host system will do the same. Hence there's nothing to prevent the pullup from pulling up.

The last half of cycle 2 seems strange, though. In the no-pullup frame we see the voltage drop sharply at the end (late in period 2b). Although it's slightly OT, I'm puzzled and bothered by this. It suggests something odd about the device, something odd about your wiring or the way the experiment was done, or something I'm missing or don't understand.

Just checking - you said the blue curve is the TMS9929's /CSR pin. Is that the device's chip-select input? Can you post or link to a datasheet for that chip? And did I get Phase2 in the correct relation to the other waveforms? Edit: alternative Phase2 interpretation added.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

In version 2 of the animation above I shifted the clock, and the result seems more plausible in some ways and less so in others.

I put two arbitrary timing marks in the excerpt below, both of which seem to indicate the effect of Phase2 going high (and output drivers being enabled). But they are not separated by an integer number of cycles; there's also a roughly one-quarter-cycle phase shift. Apparently there's one output driver that responds promptly to Phase2 going high, and another which for some reason is very sluggish to do so -- at least that's one possible explanation.

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Hi,

the heat wave in Germany gives me a break today, so I'll try to clarify some stuff I should have been more specific about earlier.
First, here is the datasheet for the TMS9929. /CSR is the chip select input for reading, there is a separate one, /CSW, for writing.
http://www.datasheetarchive.com/dlmain/Datasheets-23/DSA-445645.pdf
Second, /CSR or /CSW are generated only from the address lines and r/W, there is no PHI2 involved.
I attached another graph to show how /CSR (yellow) relates to PHI2 (blue).

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?