I recently built a sound card with an AY-3-8912A IC on it and a little programmable logic to make it fit into my homebrew computers address space.

Unfortunately, it doesn't work properly. I somehow missed a timing requirement such that my system is attempting to write to it's registers in an approximately 250nS window (PHI2 clock of 2MHz 50% duty cycle, disregarding propagation delays etc). It requires a tDS (Data setup) of 50nS, a tDH (Data hold) of 100nS and a whopping tDW (Data pulse Width) of 1800nS!

I'm going to re-engineer it but I would like some suggestions beyond using a 6522 Via chip which just seems to be the long way around unless I'm missing something. One thing I don't want to do is hold the clock becuase it's going to be the timebase for the video address generator when I get that far.

No need to hold the clock; you can use the cpu's RDY input instead. It wouldn't take much to hack together a circuit that generated a bunch of wait-states when the sound chip is accessed. RDY doesn't stop the clock; it just pushes the cpu's clutch pedal.

In the photo of your system I thought I saw a VIA. Assuming it has enough IO pins presently unused, I don't know why you'd hesitate to use it -- it seems like a pretty good solution to me. The VIA should be very easy to attach to the sound chip. Such a hookup could be valuable even as a temporary measure, simply soften the learning curve while you get familiar with how the sound chip reacts to all the various sequences sent to it.

A third solution is SPI, which you mentioned elsewhere was on your to-do list anyway. The SPI could attach to the sound chip using a parallel IO chip like this (datasheet attached). I'm sure there are a variety of chips that could do the job; this just happens to be one I'm acquainted with.

cheers,
Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

There is indeed a VIA chip there, however that particular one is entirely broken out to a couple of headers (same as the BBC User port) for external use. I still have plenty of address space left but am conscious of wasting it as I only allocated one page for IO which might well have been a mistake. I plan on having a maximum of 3 VIA's in the system with a backplane extender later. As for the RDY pin, I like that suggestion and hadn't thought of it. I'll have to look into that.

I guess the lack of experience is showing, but that means I'm learning and keeping PHI2 to just 2MHz for now.

EDIT: Just had a look at the datasheet you sent me and it does indeed look interesting.

Another option might be to run the data and address lines to the synthesizer through latches, allowing them to hold the signals steady while the CPU moves on. It's not like the CPU has to read the synthesizer, is it? This would also free up the data bus in case you're doing anything with the "backside" of the clock cycle, such as fetching your video data stream.

I have considered latches and have quite a large pile of 'em to choose from and indeed you DON'T need to read from an AY-3-8912A to make noises. You only need to read if you're using the spare IO for input. Since I used programmable logic for converting between the 6502's bus and the requisite signals for the AY, I'm considering changing the HDL code too. I feel sure I should be able to create a little RDY hold counter in a GAL22V10 though for the life of me I can't think why it has to be so much harder than in Verilog.

If a simple tacking on of a couple of wires and a quick change of code were all that were needed I'd be chuffed to bits but frankly I can imagine it being a new board. Shame as it's the first board I've ever made using photographic methods instead of the wallet burning Press'n'Peel.

Once again, Thankyou to the community here for your valuable and educational input. I'll check in again tomorrow morning about at about 0800Z.

I'm considering using a 74HC123 Monostable IC to generate the pull on the RDY line. Can anyone see a good reason why this won't work or might cause problems?

It's a creative solution, and it will work, but it could be troublesome. That's because there is a brief time slot once each cycle during which RDY is not allowed to change. You need to respect the setup & hold times for RDY, namely tPCS & tPCH.

For your sound chip you want RDY to go low and stay low for a given number of cycles. But the monostable will keep RDY low for a certain number of microseconds, plus or minus a percentage of error -- say 10 or 20%. When you're aiming for a one-cycle delay it's easy to tolerate 20% unpredictability and still avoid the forbidden time-slot(s). 20% of one cycle is a small error. But I think you said your sound chip needs not one but a handful of waitstate cycles. 20% variation of that delay is too much variation for safety.

With precision RC components you can reduce the percentage of variation but that only gets you so far. As you seek longer delays, at some point you'll be forced to adopt a digital timer instead (which always resolves to an exact integer number of CPU clock cycles).

HTH,
Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

So what you're saying is that I either need to do it all digital, make things synchronous with a flip flop or chase a different approach.

You have various options. But in your case it does not matter as you only write data. You only need to consider the setup and hold time when asserting RDY so the very cycle that accessses the sound chip is strechted. So when you trigger your one shot you must make sure that propagation delay from the trigger to output asserts RDY long enough 10ns before PHI2 transitions from high to low. Once the one shot times out it is not important to honour setup time for RDY as you write data and the sound chip will take the data when RDY is de-asserted. The worst case is that your 6502 cycle will be stretched for an additional cycle and I assume this is not critical in your application

cheers

Peter

Right. The issue with the monostable can be corrected if its output goes to a flip flop and from there to the RDY input. The flip flop gets clocked on the rising edges of Φ2, and changes in the signal sent to RDY can only occur in the instant following the start of phase two (never in the time slot that defines a violation).

In years gone by I would've agreed with this conclusion, but recently I learned how my view of the matter was incorrect (at least in the case of something as complex as a microprocessor). It would seem that violating the setup & hold times merely makes it questionable whether another wait state will occur. IOW, one might expect two possible outcomes -- a coin toss, heads or tails. (And in DigitalDunc's case both outcomes are acceptable, as an extra wait state is harmless.)

What this overlooks is the strong likelihood that RDY connects to various sections inside the cpu chip, and, gated with other signals, will influence the next state of several flip flops. Violating setup & hold times produces a risk the various flip flops will fail to properly coordinate what the chip does next. IOW there are more than two possible outcomes. And the outcomes in which RDY is taken to be high -- yet also low -- will not be satisfactory.

cheers,
Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

What datasheet for the AY-3-8912A are you using? The ones I've got specify a minimum write data pulse time of only 500nS (for example, see http://www.ym2149.com/ay8910.pdf).

I've never had any problems writing directly to these devices from a 1MHz or 2MHz 6502 with the chip directly connected to the CPU bus and no wait states - working at 2MHz obviously hugely violates the write data pulse time but I've never had any problems with over a dozen different AY-3-8910's and AY-3-8912's, so I guess the data sheet value is very conservative. Either that, or newer versions are faster than the original devices. All the devices I've used have 1980's date codes on them.

If you are not getting any output from the chip, check the following first before you try slowing down your processor.

What combination of control signals are you feeding the AY-3-8912A chip? I've always used the following.

BC2 = tied high

BDIR & BC1 are normally low.

Write data = pulse BDIR high
Write address = pulse BDIR & BC1 high

I've never read back from the PSG but pulsing just BC1 high should make it output register contents on its data bus.

These pulses should be generated when the 6502 addresses the PSG and phase-2 is high.

Also, if the chip does not seem to be generating any output, remember that the analog outputs are current outputs, not voltage outputs. Without a resistor from the analog outputs to ground, the chip won't generate any output! I couldn't find a suitable value given in the data sheet but I recall using 4.7k resistors when I've used these devices - I'll have to check to confirm this, however.

Don't forget that writing to a register is a two-stage process, first you must write the register address, then you must write the data itself.

And don't forget that register 7 needs to be written to to enable the sound channels before the chip will do anything!

As a quick test, the following should generate an output on chanel 1.

Write 0 to reg 0
Write 4 to reg 1
Write 254 to reg 7
Write 15 to reg 10

I appologise if I'm telling you things you already know, but these points cover the problems I encountered when I first used an AY-3-8912. I hope you find them useful.

Edit - Another Idea

As you say there is no nead to read from the PSG, you could always use a latch to latch the data written to it and a monostable to extend the BDIR and BC1 pulses to meet the PSG's timing requirements. This would avoid slowing down the CPU and would still remain effective if you decided to increase your CPU's clock speed later. At high clock speeds, this would mean you eed to watch how often you write to the PSG - the CPU might have to wait until the previous write was finished but at 2MHz, the write pulse should be over before the 6502 can grab another value to write to the PSG EDIT I see nyef also suggested this.

_________________
Shift to the left,
Shift to the right,
Mask in, Mask Out,
BYTE! BYTE! BYTE!

It would appear that I have a mix of AY-3-8912's and AY-3-8912A's from different manufacturing dates including a couple of bad copies from god knows where. I have indeed been getting sound from it but the registers behaved oddly. Also I originally forgot to include the signal nIOSEL (My signal indicating that the hardware page C0xx is being addressed) originally and that caused bus contention and wacky crashes. There seem to be a few subtle changes under the hood between the A and non A versions as evidenced by the differing timing constraints. I'm using some of the ideas you've all thrown up and I'll hopefully have something to show for it by supper time tonight.

Wish me luck! If it works, I'll be making it play Axel-F. (Or I'll be sulking till next weekend)

If this is your concern, then just add a flip-flop and a AND gate. "AND" the outputs of the one-shot and the flip-flop (74HC74 or equivalent) and feed this to RDY. Connect the clock of the FF to PHI2 and the D-input to the output of the one-shot.

Good point about the AND gate, Peter -- that's something I overlooked in my previous post (when I discussed adding a flip flop so the one-shot could be used).

Hmmm. If the flip flop has Set\ and Clear\ inputs (like a 74xx74, for example), the circuit could be rearranged so a separate AND isn't required. Q\ of the one shot drives Clear\ of the FF. Q of the FF drives RDY. The FF clock comes from Φ2, and D is tied high.

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Not sure exactly what the suggestion is, but take care that you don't clip one edge or the other into a runt. Generally, to synchronise, you need to incur a delay. I notice in visual6502 that the RDY input signal goes in two directions: one is synchronised through a flop of some sort, the other is routed to a combinatorial gate in the middle of the chip.