I did look into Acorn's two emulators: the 65Host and 65Tube programs, using the excellent disassembler
Armalyser - it's amazing how dense the ARM instructions are, and very useful that the machine is so like the 6502. 65Tube is the faster of the two: it keeps the 6502 registers in ARM registers and handles PC and SP as pointers into a byte array. Each opcode finishes with a fetch and a computed jump, into a table of 16-word sections, one per opcode. For example, the code for BCC is just 6 istructions:
Code:
; handler for 0x90 BCC
LDRCCB R0,[R10],#1 ; fetch the operand byte
MOVCC R0,R0,LSL #24 ; shift left to prepare sign-extension
ADDCC R10,R10,R0,ASR #24 ; adjust the PC for branch-taken case
ADDCS R10,R10,#1 ; increment PC for branch not taken
; standard postamble: fetch next instruction. R10 is the 6502 PC, as a byte pointer
LDRB R0,[R10],#1 ; ifetch into R0 and PC++
ADD PC,R12,R0,LSL #6 ; computed jump to next opcode handler
Notice how the predicated instructions remove the need to branch, and how the ARM's own carry flag serves to emulate the 6502's - same for N, Z and V. All the 6502 state is held in registers throughout. The free shifts, auto-increment and the
familiar-looking address modes help a lot too.
I wanted to come back to one of Ed's observations from a few years ago.
I've also just been disassembling 65Tube, and it looks like a very efficient 65C02 implementation in ARM.
I'm thinking of trying to reverse engineer the 65C02 core of this back into a buildable source form.
I was also wondering if the original sources were ever released? I did have a poke around the
, and couldn't find anything.