cbscpe wrote:
You could use a dual-rate clock. After a reset the CPU runs at half the speed and the ROM region really selects the ROM. The reset routine copies the ROM to the RAM which overlays the ROM.
The ROM-to-RAM copy approach has some interesting advantages. But sometimes we want to "just make the darn EPROM work"! -- using the simplest means possible.
Generating wait states:
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simple wait-state generator.gif [ 4 KiB | Viewed 9247 times ]
The circuit above generates a one-cycle-long wait state when the EPROM is accessed. (For WDC, it's best to add a series resistor -- see below.) One wait state may not sound like much; but, when you're pushing the CPU close to its maximum clock rate, adding
one wait-state roughly
triples the time available for the EPROM to respond! Here's why. At high clock rates tADS and tDSR delays (which each consume a fixed number of nanoseconds) end up accounting for about 50% of all the nanoseconds in a clock cycle. (65xx timing is graphically explained in the
Visual Guide to 65xx CPU Timing).
The access time remaining for memory to do its job works out to roughly 50% of the nanoseconds in one clock cycle. Adding a one-cycle-long wait state changes this figure from
50% to
150%. (The tADS and tDSU delays don't get applied again when a wait-state cycle is inserted.) Stated another way, if the cycle time is 100 ns, say, then adding a one-cyle-long wait state increases the available memory access time by 100 ns.
-- Jeff
ETA: There's an implicit assumption. The circuit only works if
/CS goes low before the rise of Ø2 -- which is normally the case. BDD touches on this in the following post. Also: using the both halves of the '109,
two wait states can be provided (see circuit below). The extra access time thus provided will be 200% of one cycle. The total access time will be about 5 times what's available using no wait states.
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double-wait-state generator.gif [ 4.32 KiB | Viewed 9234 times ]
Further edit: in contrast to Rockwell and other suppliers, WDC makes the RDY pin bi-directional. A WDC 'C02 or '816 will pull its own RDY pin low as a result of executing a WAI instruction. This can result in excessive current flow if the RDY pin is driven high by external logic at the same time.
One solution is to use an Open-Collector or Open-Drain gate to drive RDY (as shown in the upper diagram in image below) but this limits the ability for RDY to quickly return high. It's better to use an ordinary gate and simply include a series resistor to limit current flow (lower diagram).
WDC's datasheet was revised to include a comment about the series resistor (as well as a comment about pullup resistors).
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bi-directional RDY - WDC caveat.gif [ 12.97 KiB | Viewed 9002 times ]
Unfortunately WDC doesn't suggest a value for the series resistor, so let's look at that question. Too low a value means increased dissipation, and the risk that a valid logic-low voltage won't be achieved. OTOH too high a value will produce unacceptable delay re the RC of the gate and resistor driving the capacitance of the RDY input. I myself would use a series resistor of around 470 ohms -- a rather low value, but IMO not so low as to prevent a valid logic-low voltage from being achieved. In
another thread Garth suggests putting a small (~22 pF) capacitor in parallel with the resistor, which allows use of a much higher resistance but of course increases the component count slightly.
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bi-directional RDY re WDC 02 and 816.gif [ 9.15 KiB | Viewed 9099 times ]
_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
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