Hello,

Could someone direct me to references on how to use the COP instruction and on how the VDA, VPA, VPB, and Abort lines are typically used?
There is an abundance of information on 65C816 programming but there seems to be very little on the hardware use.

_________________
65C02 Country

It has been several days and no one else has jumped in, so I'll try to help stir up some discussion with my ignorance.

Do you need more info than what's in the data sheet? It seems rather clear to me, but I don't have the experience with these signals to add any further insights. Unfortunately WDC is not good about putting out application notes. We're kind of generating those as we go along here at this website.

According to the programming manual, the Abort\ interrupt would typically be asserted by external hardware if you try to access an address where nothing is installed, or if you have some kind of memory-protection hardware and the address is not valid for the currently executing task, or if a parity error is found in the memory read. To operate properly, this input should only be kept low for one cycle at a time. The instruction that was executing when Abort\ was asserted does not get completed-- hence that very instruction is aborted without affecting any registers, so it's the instruction itself that's aborted, not just the program flow following that instruction as would be the case with other interrupts.

There are a few forum members here who could probably shed some light on effective ways to use DMA, virtual memory, data and program caches, and hardware interrupt-prioritizing with the VDA, VPA, and VP\ signals you mention. However, a 65-family attraction is the good amount of computing power for a simple system that does not require a computer scientist to understand as the high-end processors nearly do with their caches, virtual memory, memory protection, deep pipelining, coprocessors, DRAM controllers, and other complexities as well as the hardware requirements that go with some of these features.

From the programming manual, the COP instruction looks like you could use it like another BRK instruction with its own vector if you wanted to. I don't see any reason you couldn't make your own use of it if you don't have a coprocessor. However in my estimated 50,000-100,000 lines of 65-family programming, I personally have never had any occasion to even use BRK except in that first class in school in 1982 where we had AIM-65's in the lab and we ended our short hand-assembled routines with BRK. The manual implies there could be a coprocessor that could trap the op code and take over in hardware if you don't turn control over by way of your program pointed to by the COP vector.

I would be interested in seeing more discussion on these things. If you end up successfully implementing them, write it up for Mike to put in the projects pages on this website.

Thanks for the reply.

I've gained a little more knowledge about the subject since the posting.
As you wrote, BRK and COP are identical except for the vector address.
What I didn't know was that the signature byte is loaded into the stack.

As for the 65C816 control lines, I was wondering for example if one could use the VPA line to access the upper 65K of 128K memory instead of physically using the program bank reg. That way there could be 65K for data and 65K for program with just one 128K memory with a 65K system. Or am I just nuts?

Greg

_________________
65C02 Country

All four combinations of VPA and VDA high and low are meaningful. It looks like you can tell instructions' operands from data; but if you're not implementing cache or DMA or VM, I don't yet see any reason to implement the extra hardware to do what you're talking about. It looks like you're trying to avoid latching the extra address bit at each phase-2 rising edge, but I think this latching would be easier. I think you could do a better job of your two-bank system by using the program bank register K and data bank register B, which are part of the 65816. Then if you're going to go that far, you might as well get a 512Kx8 SRAM for $10 in a 32-pin DIP instead of using a 128KB SRAM. I have a Forth kernel written and working for the '816, but I've made it all work in bank 0 so far and plan to only access non-0 banks for tables and other data by using long addressing. (I don't have hardware built to do that on yet.) Forth is so memory-efficient that it's got to be quite a whopper of a program to need more than one bank, although I have uses in mind for at least a couple of extra megabytes for data. Then of course there's the possibility of using different banks for different concurrently running programs too, so each program can start at address 0 regardless of what else is loaded. No MMU required.

I agree Garth

I'm just looking for ways to keep glue logic reduced to a minimum. For example, with an Altera CPLD and using the 65C02 the least pin count device can be used to take care of memory and have pinout room for up to eight 16 byte blocks for I/O but if address/data demultiplexing plus extra address lines are required the next Altera CPLD physical size would be nearly doubled.
I think that this is a good subject to discuss.

Greg

_________________
65C02 Country

If I'm understanding what you're saying, it's not as complicated as that. If you just want one more address line for 128K, all you need is one flip-flop bit. Its data input goes on D0, its output is A16, and its gate on phase 2. When phase 2 is low, it's transparent, and when it's high, it's latched. If you want the entire high address byte (A16-A23) you just use an 8-bit latch, like the '573. This is simpler than trying to use VPA and VDA (unless you want to do more than just add more 64K sections of memory).

As for address decoding, almost every scheme someone posts here is far more complex (and slow) than it needs to be. If you can get by with 16K of RAM and 32K of ROM (or vice-versa) and no more than ten I/O ICs on a 6502 system, you can do it all with 3/4 of a single 74xx00. See http://www.6502.org/users/garth/project ... chematic=2 . (One of my inverters could be replaced with a NAND. The other one pointing to the left was for something I never carried out, and now I can't even remember what it was.) That means a 74ACT00 was not only enough, but even leaves a section available for something else.

Okay, can't argue with that at all. I have alway forced myself to keeping the I/O in zero page specifically 80-ff which complies with WDCs development stuff.
I may reconsider after seeing your logic. I will get back with you on it after I've had time to study it in detail.

_________________
65C02 Country

Garth

I have run into problems in the past by not gating 02 with R/W to obtain OE and WE. The new W65C22s IRQ can't be wire ORed and non 65xx devices often require seperate read write lines (OE and WE again).

You are right of course about don't complicate things if not needed and from personal experience speed is sacrificed.
I spent a lot of time deciding wether or not to try programmable logic and it is the route that I took. It is what I will use for the 65C816. So far, free design software is still available for the popular programmable devices including schematic entry.

Greg

_________________
65C02 Country

Darn-- I tried entering a special character the normal way for E-mail and the forum software (or maybe IE) dumped everything I wrote, so I have to start over.

> I have run into problems in the past by not gating 02 with R/W to obtain OE and WE.

The RAM select, or at least the write enable, needs to be gated by phase 2, since the processor spec.s do not guarantee that the address will be valid and stable anytime before R/W\ goes down. Not gating it like this can result in writing to unintended addresses. Those addresses may not be needed or read anytime soon, but eventually there will be trouble. The 65c22 VIA won't work though unless the CS1, CS2\, and R/W\ are correct well before phase 2 rises. The circuit mentioned above takes care of this.

I would be interested in what other peripherals you would like to interface. The VIA is very versatile, but there is no 65-family periperal that directly interfaces to something like SPI, I²C, USB, etc.. It's easy to bit-bang the first two, but it would be nice if more were available with everything taken care of in hardware.

As for your last previous post-- Don't forget the '816 also allows you to move the "zero page" (ZP)-- called "direct page" (DP) on the '816-- around as often as you wish in your programs. I'm not too crazy about WDC's memory map though. It may be why their '265 is only rated for half the speed their '816 is rated for.

What kind of logic programmer do you have, and how do you like it?

Garth

First please except my apology for seeming like I was rejecting your experience and wisdom. The Word says that those who reject wisdom are in trouble.

>What kind of logic programmer do you have, and how do you like it?

I have been learning to use the Max+II software from Altera and have done a few designs mostly just for learning, things like programable 16 bit counters, programable I/O, edge detectors with interupt flags.
Although they want you to use HDL tools, schematic entry is good for old school like me. The waveform editor works very well for simulation testing.

>I would be interested in what other peripherals you would like to interface.

Basicly anything that the 6522 is not good at, UARTs mostly I guess.
My current interest is RF RS232 data links, tiny internet modems.
The 65xx SBC that I'm developing now will do remote measurement and control.
I've done a little work on ethernet interface.
USB has really taken over in the PC market but I haven't checked into that much.

Greg

_________________
65C02 Country

> I have been learning to use the Max+II software from...

How about the programming hardware though? Data I/O? Bytek? Logical Devices, Inc.? HTE? Link? Needham's? (My list of device programmer manufacturers may be outdated. My own EPROM programmer is made by Needham's.)


> Basically anything that the 6522 is not good at, UARTs mostly I guess.

You can still get 65c51's, but it's getting harder and harder since no one is making them right now, and the fastest ones were only 6MHz (from CMD, before they dropped a list of hundreds parts a couple of years ago, including their 65 line). Supposedly WDC is going to start making it again, but they're far behind the schedule they gave a year or two ago. The Maxim MAX3100 is a nice SPI-interfaced UART, with IrDA capability too, all in a 14-pin DIP. I've interfaced it through a few pins of a 65c22. (Being SPI, you coud interface a ton of them through the same 6522.) Another part, the MAX3110, even has the line drivers and receivers built in, saving more board space.

I have kept putting off getting into programmable logic myself for several reasons, each one only half valid. I started getting into VHDL and Cypress CPLDs a few years ago for a project at work, but that project got cancelled. I still have Cypress's Warp software and CPLD programmer for in-circuit serial programming using JTAG, IIRC. Although that's apparently the common way to program the CPLDs and FPGAs, I don't know if many of the smaller PLDs (GALs, etc.) can be programmed that way.

I would like to make something like the 6522 with some additional capabilities, like the different serial interfaces (especially SPI and I²C). Then of course my imagination starts going to making another 65-family processor, but that's a huge project.


> I've done a little work on ethernet interface.
> USB has really taken over in the PC market but I haven't checked into that much.

Take a look at the little module at http://www.instantusb.com . I haven't used it, and I don't know if it can make your home-made computer a USB host; but it might be worth a look.

>How about the programming hardware though?

They require an interface called a byte blaster or bit blaster. I got mine free but there is someone I think who posted a schematic on 6502.org that is identical to mine.

>You can still get 65c51's

Speed is the main reason That I don't use 65c51s. I've settled for a dual uart from Philips but that's not in concrete yet. I'll check out the Maxim stuff.

>I would like to make something like the 6522

I did a fancy design with a lot of 6522 type stuff in it but ran into the problem of cost. An FPGA was required and a pretty expensive one at that.
I too have had thoughts of building my own 6502 type processor but truhtfully I don't know enough to even get started. A true 16 bit data bus 6502 would be nice.

Greg

_________________
65C02 Country

Okay, I have a 65C02 SBC design which has been completed and proven in a real circuit board. Now I am redesigning it removing some things and adding some things. I feel that it should be made 65C816 compatible or maybe even strictly 65C816. The board is all surface mount. Size is 2.8 x 4.0 inches because that's the largest you can go with the free eagle.
The new design currently has two 32k of eeprom shadowed ram which has a 25ns access time, four 16 byte blocks of I/O in upper zero page with three 65C22s and a dual uart. One uart is for RS232. The other is for a modem. All glue logic is in a cpld. The throughput of the cpld is 5ns.
Programs can be initially installed in circuit with a parallel prom programmer.
The board design is actually complete in Eagle. I'm just trying to find a way to incorporate the 65C816. The only thing that I have been able to come up with is get rid of the cpld and a 65C22 and use regular logic chips.
The timers in the 65C22s are very valuable and the regular logic would slow things down.

Greg

_________________
65C02 Country

> The only thing that I have been able to come up with is get rid of the
> cpld and a 65C22 and use regular logic chips.

Is that for lack of room? You can make the '816 go in the same socket or space as the '02 (in PLCC or PQFP) and use a few jumpers to select which processor you're using. There is no need to forfeit your other features.

Yes, it is for lack of room. The plan is to make the 65C02 and 65C816 interchangable. The problem is that the foot print of the cpld can't be any larger than that of the processors and 65C22s. Every available I/O pin of the cpld is occupied for the 65C02 glue logic. If I am to demultiplex any bank address of the 65C816, a 65C22 or the parallel interface dual UART will have to be deleted which will free up an address select line and an interupt line from the cpld. Three 65C22s aren't really vital. Many applications can be done with two. A serial dual UART is possible but I would have to study the throughput of the serial interface.

Greg

_________________
65C02 Country