after many suggestions by BDD I finally took the step and decided to go with those fancy ATMEL CPLDs available for 5V and as expected I start having some questions. But first let's talk about my environment. So far I have some of these PL-44 http://www.futurlec.com/PLCC_Adapters.shtml the ATMEL USB progamming cable from here http://www.kanda.com/CPLD-Programmers.175.html. As always deliveries from UK to CH are a pain ... they are expensive and take a long time, not only because of parcel service but mostly because of swiss customs, but I wanted to get a genuine one and not a fake from china. At the end it cost me the double as listed on the vendors page. But that's not his problem, thats mainly because Switzerland is not EU
. And last but not least a few ATF1504AS10JC44 to play with. I have installed ATMEL ISP and it recognizes the cable.
- ATMEL ISP successfully detects programming cable
Code: Select all
Name AppleIIe-IO ;
PartNo 00 ;
Date 18.04.2015 ;
Revision 01 ;
Designer Engineer ;
Company company ;
Assembly None ;
Location ;
Device f1504plcc44 ;
/* *************** INPUT PINS *********************/
PIN 1 = !RES ; /* */
PIN 2 = A0 ; /* */
PIN 3 = A1 ; /* */
PIN 5 = A2 ; /* */
PIN 6 = A3 ; /* */
PIN 7 = A4 ; /* */
PIN 8 = A5 ; /* */
PIN 10 = A6 ; /* */
PIN 11 = A7 ; /* */
PIN 12 = OA ; /* */
PIN 13 = CA ; /* */
PIN 14 = RW ; /* */
PIN 15 = !IO ; /* */
PIN 18 = PHI2 ; /* */
PIN 19 = KEY ; /* */
/* *************** OUTPUT PINS *********************/
PIN 20 = TEXT ; /* */
PIN 21 = MIXED ; /* */
PIN 22 = PAGE2 ; /* */
PIN 23 = HIRES ; /* */
PIN 25 = RAMRD ; /* */
PIN 26 = RAMWR ; /* */
PIN 27 = CXROM ; /* */
PIN 28 = C3ROM ; /* */
PIN 30 = ALTZP ; /* */
PIN 31 = STO80 ; /* */
PIN 32 = COL80 ; /* */
PIN 33 = ALTCH ; /* */
PIN 34 = ROMRD ; /* */
PIN 38 = RDLCR ; /* */
PIN 42 = BANK2 ; /* */
PIN 43 = DOUT ; /* */
PIN 44 = !KBD ; /* */
/* *************** PINNODES *********************/
PINNODE = STRB ; /* */
PINNODE = ANN ; /* */
PINNODE = INP ; /* */
PINNODE = INPA ; /* */
PINNODE = RAMPR ; /* */
PINNODE = K7 ; /* */
PINNODE = TEMP2 ; /* */
PINNODE = TEMP3 ; /* */
/* Declarations */
K7 = K7 & !RES & A7 /* Keep when A7 = High */
# K7 & !RES & A6 /* or A6 = High */
# K7 & !RES & A5 /* or A5 = High */
# K7 & !RES & !A4 /* or A4 = Low */
# K7 & !RES & A3 /* or A3 = High */
# K7 & !RES & A2 /* or A2 = High */
# K7 & !RES & A1 /* or A1 = High */
# K7 & !RES & A0 /* or A0 = High */
# K7 & !RES & !PHI2 /* or PHI2 = not asserted */
# K7 & !RES & !IO /* or IO = not asserted */
/* clear on $C010 with PHI2 = high */
# KEY ; /* set when key is waiting */
FIELD ADDRESS = [A7..0];
FIELD RDSSW = [DOUT];
Table ADDRESS=>RDSSW {
[00..0F] => K7;
[11] => BANK2;
[12] => !ROMRD;
[13] => RAMRD;
[14] => RAMWR;
[15] => CXROM;
[16] => ALTZP;
[17] => C3ROM;
[18] => STO80;
[1A] => TEXT;
[1B] => MIXED;
[1C] => PAGE2;
[1D] => HIRES;
[1E] => ALTCH;
[1F] => COL80;
[61] => OA;
[62] => CA;
}
Code: Select all
77: [00..0F] => K7;
[0002ca] invalid number: K7cheers
Peter
. I successfully programed and verified the chip and now I'm debugging my design. So far I found that the way I generate clock for internal flip-flops is somewhat not correct, I wanted to qualify it with PHI2 but it seems I screwed up the equation (I don't show it now, because I'm sure the mistake I have here is so basic that I would be ashamed to ask, I need to fix that myself). As you see the design uses all but one pin with the JTAG pins unused. So I can always go back using ISP. 
