Hi BDD,
so far I have some success (or I should say I made a big step forward). The reasons for my problems (except one that I have to address now) were the following.
Fields are numbered from right to left as already pointed out by 8Bit. So the following do really select the correct address or address ranges.
Code:
FIELD ADDRESS = [A7..0];
Table ADDRESS=>DOUT {
[00..0F] => 1 & K7;
[11] => 1 & BANK2;
[12] => 1 & !ROMRD;
Also you need to have as many "fixed" bits (a constant of appropriate length) on the output side as you have in the table statement. Because you create the same number of outputs in all statements. In my case I have one output (DOUT) so I must always select it. If you want to make a n-to-1 multiplexor you need then to add the signals after the bit fields. In the other thread with the input from 8Bit banedon did show that very nicely (
http://forum.6502.org/viewtopic.php?f=10&t=3257&start=15#p37410). This makes address decoders very easy to read in fact. I think fields and tables do work.
Then one huge problem with WinCUPL, once you have opened one of the result files (e.g. .fit or .io) he does not update the screen when you re-compile the design so what you see on the screen is the previous result. You need to close the window and then select the file again, that explains the problems that I was thinking the fitter did something wrong. So now before compiling a design I close all files or even re-open the project to make sure I have a fresh start on the display.
So now I have my design with the pins allocated by the fitter as follows
Code:
B
D A
O V R K G N
A A U C A E E N K O
3 0 T C 6 S Y D 2 A
____________________________________
/ 6 5 4 3 2 1 44 43 42 41 40 \
TDI | 7 39 | CA
A7 | 8 38 | TDO
RW | 9 37 | PHI2
GND | 10 36 | IO
A5 | 11 35 | VCC
A4 | 12 ATF1504 34 | A2
TMS | 13 44-Lead PLCC 33 | A1
WRRAM | 14 32 | TCK
VCC | 15 31 | ROMRD
ALTZP | 16 30 | GND
ALTCH | 17 29 | MIXED
| 18 19 20 21 22 23 24 25 26 27 28 |
\____________________________________/
C C C H G V S T R P R
3 X O I N C T E A A A
R R L R D C O X M G M
O O 8 E 8 T W E R
M M 0 S 0 R 2 D
And I now I find my A3 and the other signals
. I successfully programed and verified the chip and now I'm debugging my design. So far I found that the way I generate clock for internal flip-flops is somewhat not correct, I wanted to qualify it with PHI2 but it seems I screwed up the equation (I don't show it now, because I'm sure the mistake I have here is so basic that I would be ashamed to ask, I need to fix that myself). As you see the design uses all but one pin with the JTAG pins unused. So I can always go back using ISP.
So far what I can say, everything is straight forward and I spent much less time than anticipated to get this far. Now I just have to order the TQFP-44 versions and solder them on my DIP-48 adapters to make efficient use of bread-board space.
I have one question, once you use the TDI, TDO, TCK and TMS pins for your design you can't program the chip using ISP anymore? Is that correct? What do you do then? Is there a way to at least clear/reset the chips without a professional (aka rather expensive) programmer?
cheers
Peter
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. And last but not least a few ATF1504AS10JC44 to play with. I have installed ATMEL ISP and it recognizes the cable. 
