cbscpe wrote:
Hi Banedon,
any reason why you connect the '259 to the VIA port, it's actually a waste of VIA pins in my opinion. I always use them as they have been used in the Apple II computer. You need a /SEL which is qualified with PHI2 and covers a range of 16 addresses. Then I connect D -> A0, S0 ->A1, S1 ->A2 and S2 -> A3. /CLR is connected to /RES so you have a clear initial state. Then a simple LDA instruction can throw any of the flip-flop in the '259.
cheers
Peter
Hi Peter
It's mostly because I want to keep things off the 6502 address and data buses as much as possible. That way if I really need to put something on them then I don't have to worry about having already overloaded them.
But going with your idea, is this what you're suggesting? The only part I'm a bit uncertain of is where /SEL comes from. I assume a VIA pin as in my circuit diagram (please ignore it saying PA0- it should say PB0)?
If so, then surely then you have a disjunction between the right address being on the address bus and /SEL (/LE) going low.
Attachment:
latch_from_addrbus.png [ 14.55 KiB | Viewed 1127 times ]
[EDIT] ...or would use use the decoder to intercept a certain range (as small as possible) and then enable the latch select (/LE) pin? I'd have to introduce mode address pins if I did that to avoid wasting massive amounts of address space.