Ok here we are with the dual read bank, write bank implemented (Many thanks to Peter).
I get an odd error with this, though, when trying to simulate it. It seems to generate a parse error in the .SO file when compiled from WinCUPL. If I then go into the Simulator and compile it I end up with what I expected.
Here's the code and the data I ran it with. Can anyone else reproduce the error?
Code:
Name AddressDecoder;
Partno Lattice22V10B;
Date 02/04/15;
Revision 01;
Designer shalewyn.com;
Company shalewyn.com;
Assembly XXXXX;
Location XXXXX;
Device g22v10;
/*
* Lattice GAL 22V10B pinout, DIP, top view
*
* I/CLK.[ 1 24 ].VCC
* I.[ 2 23 ].I/O/Q
* I.[ 3 22 ].I/O/Q
* I.[ 4 21 ].I/O/Q
* I.[ 5 20 ].I/O/Q
* I.[ 6 19 ].I/O/Q
* I.[ 7 18 ].I/O/Q
* I.[ 8 17 ].I/O/Q
* I.[ 9 16 ].I/O/Q
* I.[ 10 15 ].I/O/Q
* I.[ 11 14 ].I/O/Q
* GND.[ 12 13 ].I
*
*
*
* $1000-$1FFF BaseRAM %0000 0000 0000 0000 - %0001 1111 1111 1111
* $2000-$7FFF SwapRAM %0010 0000 0000 0000 - %0111 1111 1111 1111
* $8010-$801F VIA #1 (I/O) %1000 0000 0001 0000 - %1000 0000 0000 1111
* $8020-$802F VIA #2 (I/O) %1000 0000 0010 0000 - %1000 0000 0001 1111
* $8040-$804F ACIA (I/O) %1000 0000 0100 0000 - %1000 0000 0010 1111
* $9000-$FFFF ROM %1001 0000 0000 0000 - %1111 1111 1111 1111
*
*
*
* Inputs
*/
/* Inputs */
PIN 1 = PHI2;
PIN 2 = R_W;
PIN [3..6] = [A15..12];
PIN [7..9] = [A6..4];
PIN 10 = sbR0;
PIN 11 = sbR1;
PIN 13 = sbW0;
PIN 14 = sbW1;
/* Outputs */
PIN 15 = !RD;
PIN 16 = !WR;
PIN 17 = !IO;
PIN 18 = !BASERAM;
PIN 19 = !SWAPBANK0;
PIN 20 = !SWAPBANK1;
PIN 21 = !SWAPBANK2;
PIN 22 = !SWAPBANK3;
PIN 23 = !ROM;
/* Main */
RD = PHI2 & R_W;
WR = PHI2 & !R_W;
BASERAM = !A15 & !A14 & !A13;
SWAPBANK0 = !A15 & !A14 & A13 & !A12 & !sbR0 & !sbR1 & WR
# !A15 & !A14 & A13 & A12 & !sbR0 & !sbR1 & WR
# !A15 & A14 & !A13 & !A12 & !sbR0 & !sbR1 & WR
# !A15 & A14 & !A13 & A12 & !sbR0 & !sbR1 & WR
# !A15 & A14 & A13 & !A12 & !sbR0 & !sbR1 & WR
# !A15 & A14 & A13 & A12 & !sbR0 & !sbR1 & WR
# !A15 & !A14 & A13 & !A12 & !sbW0 & !sbW1 & !WR
# !A15 & !A14 & A13 & A12 & !sbW0 & !sbW1 & !WR
# !A15 & A14 & !A13 & !A12 & !sbW0 & !sbW1 & !WR
# !A15 & A14 & !A13 & A12 & !sbW0 & !sbW1 & !WR
# !A15 & A14 & A13 & !A12 & !sbW0 & !sbW1 & !WR
# !A15 & A14 & A13 & A12 & !sbW0 & !sbW1 & !WR;
SWAPBANK1 = !A15 & !A14 & A13 & !A12 & !sbR0 & sbR1 & WR
# !A15 & !A14 & A13 & A12 & !sbR0 & sbR1 & WR
# !A15 & A14 & !A13 & !A12 & !sbR0 & sbR1 & WR
# !A15 & A14 & !A13 & A12 & !sbR0 & sbR1 & WR
# !A15 & A14 & A13 & !A12 & !sbR0 & sbR1 & WR
# !A15 & A14 & A13 & A12 & !sbR0 & sbR1 & WR
# !A15 & !A14 & A13 & !A12 & !sbW0 & sbW1 & !WR
# !A15 & !A14 & A13 & A12 & !sbW0 & sbW1 & !WR
# !A15 & A14 & !A13 & !A12 & !sbW0 & sbW1 & !WR
# !A15 & A14 & !A13 & A12 & !sbW0 & sbW1 & !WR
# !A15 & A14 & A13 & !A12 & !sbW0 & sbW1 & !WR
# !A15 & A14 & A13 & A12 & !sbW0 & sbW1 & !WR;
SWAPBANK2 = !A15 & !A14 & A13 & !A12 & sbR0 & !sbR1 & WR
# !A15 & !A14 & A13 & A12 & sbR0 & !sbR1 & WR
# !A15 & A14 & !A13 & !A12 & sbR0 & !sbR1 & WR
# !A15 & A14 & !A13 & A12 & sbR0 & !sbR1 & WR
# !A15 & A14 & A13 & !A12 & sbR0 & !sbR1 & WR
# !A15 & A14 & A13 & A12 & sbR0 & !sbR1 & WR
# !A15 & !A14 & A13 & !A12 & sbW0 & !sbW1 & !WR
# !A15 & !A14 & A13 & A12 & sbW0 & !sbW1 & !WR
# !A15 & A14 & !A13 & !A12 & sbW0 & !sbW1 & !WR
# !A15 & A14 & !A13 & A12 & sbW0 & !sbW1 & !WR
# !A15 & A14 & A13 & !A12 & sbW0 & !sbW1 & !WR
# !A15 & A14 & A13 & A12 & sbW0 & !sbW1 & !WR;
SWAPBANK3 = !A15 & !A14 & A13 & !A12 & sbR0 & sbR1 & WR
# !A15 & !A14 & A13 & A12 & sbR0 & sbR1 & WR
# !A15 & A14 & !A13 & !A12 & sbR0 & sbR1 & WR
# !A15 & A14 & !A13 & A12 & sbR0 & sbR1 & WR
# !A15 & A14 & A13 & !A12 & sbR0 & sbR1 & WR
# !A15 & A14 & A13 & A12 & sbR0 & sbR1 & WR
# !A15 & !A14 & A13 & !A12 & sbW0 & sbW1 & !WR
# !A15 & !A14 & A13 & A12 & sbW0 & sbW1 & !WR
# !A15 & A14 & !A13 & !A12 & sbW0 & sbW1 & !WR
# !A15 & A14 & !A13 & A12 & sbW0 & sbW1 & !WR
# !A15 & A14 & A13 & !A12 & sbW0 & sbW1 & !WR
# !A15 & A14 & A13 & A12 & sbW0 & sbW1 & !WR;
IO = A15 & !A14 & !A13 & !A12 & !A5 & !A4;
ROM = A15 & !A14 & !A13 & A12
# A15 & !A14 & A13 & !A12
# A15 & !A14 & A13 & A12
# A15 & A14 & !A13 & !A12
# A15 & A14 & !A13 & A12
# A15 & A14 & A13 & !A12
# A15 & A14 & A13 & A12;
There .SI file:
Code:
Name AddressDecoder;
PartNo Lattice22V10B;
Date 02/04/15;
Revision 01;
Designer shalewyn.com;
Company shalewyn.com;
Assembly XXXXX;
Location XXXXX;
Device g22v10;
ORDER: PHI2, R_W, A15, A14, A13, A12, A6, A5, A4, sbR0, sbR1, sbW0, sbW1, !RD, !WR, !IO, !BASERAM, !SWAPBANK0, !SWAPBANK1, !SWAPBANK2, !SWAPBANK3, !ROM;
VECTORS:
1 1 0 0 1 0 1 1 1 0 1 1 0 * * * * * * * * *
1 0 0 0 1 0 1 1 1 0 1 1 0 * * * * * * * * *
1 1 0 0 1 0 1 1 1 1 1 0 0 * * * * * * * * *
1 0 0 0 1 0 1 1 1 1 1 0 0 * * * * * * * * *
And my eventual results after recompiling from within the Simulator:
Attachment:
decoder_output_success2.png [ 9.87 KiB | Viewed 1627 times ]
Confirmed as working (so far) in a GAL [EDIT] I've just removed A5-A7 (pins 7-9) as they are not used. Frees up 3 pins for future use.