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banedon
 Post subject: GAL Address Decoder
PostPosted: Thu Apr 02, 2015 9:49 pm 
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Hi guys

Here's the beginnings of my first attempt at my address decoder for my next 6502 project.
I've yet to implement the /WE out for RAM and I have a bit of an issue using the TABLE command and trying to introduce the last 4 bits of the address bus so that it tests the values properly:

Code:
Name       AddressDecoder;
Partno     Lattice22V10B;
Date       02/04/15;
Revision   01;
Designer   shalewyn.com;
Company    shalewyn.com;
Assembly   XXXXX;
Location   XXXXX;
Device     g22v10;


/*
 * Lattice GAL 22V10B pinout, DIP, top view
 *
 * I/CLK.[ 1     24 ].VCC
 *   I.[ 2     23 ].I/O/Q
 *   I.[ 3     22 ].I/O/Q
 *   I.[ 4     21 ].I/O/Q
 *   I.[ 5     20 ].I/O/Q
 *   I.[ 6     19 ].I/O/Q
 *   I.[ 7     18 ].I/O/Q
 *   I.[ 8     17 ].I/O/Q
 *   I.[ 9     16 ].I/O/Q
 *   I.[ 10    15 ].I/O/Q
 *   I.[ 11    14 ].I/O/Q
 * GND.[ 12    13 ].I
 *
 *
 *
 * $1000-$1FFF   -   %0001 0000 0000 0000 - %0001 1111 1111 1111
 * $2000-$2FFF   -   %0010 0000 0000 0000 - %0111 1111 1111 1111
 * $8000-$800F   -   %1000 0000 0000 0000 - %1000 0000 0000 1111
 * $8010-$801F   -   %1000 0000 0001 0000 - %1000 0000 0001 1111
 * $8020-$802F   -   %1000 0000 0010 0000 - %1000 0000 0010 1111
 * $8040-$804F   -   %1000 0000 0100 0000 - %1000 0000 0100 1111
 * $9000-$FFFF   -   %1001 0000 0000 0000 - %1111 1111 1111 1111
 *
 *
 * !Pin 18 - non-swap RAM   $0000-$1FFF
 * !Pin 19 - Swap bank 0 or bank 1  - $2000-$7FFF
 * !Pin 20 - /VIA 1       - $8000-$800F
 * !Pin 21 - /VIA 2       - $8010-$801F
 * !Pin 22 - /ROM         - $9000-$FFFF
 *
 *
 * Inputs
 */

Pin 1 = phi2;
Pin 2 = cpuRW;
Pin [3..11] = [A15..7];
Pin [13..15] = [A6..4];
Pin 16 = Swapbit;

/*
 * Outputs
 */

/*
 * Pin 18 = !selBaseRAM;
 * Pin 19 = !selSwapRAMbank;
 * Pin 20 = !selVIA1;
 * Pin 21 = !selVIA2;
 * Pin 22 = !selROM;
 * Pin 23 = !WE out;
*/

Pin [18..22] = [s0..4];

/*
 * Main
 */

FIELD AddressBus = [A15..4];
FIELD Selects = [s0..4];

TABLE AddressBus => Selects {
   ['H'0000..'H'1FFF] => 'b'100000; /* Non-swap RAM */
   ['H'2000..'H'7FFF] => 'b'010000; /* Swap RAM */
   ['H'8000..'H'800F] => 'b'000100; /* VIA 1 */
   ['H'8010..'H'801F] => 'b'000010; /* VIA 2 */
   ['H'9000..'H'FFFF] => 'b'000001; /* ROM */
}


Last edited by banedon on Thu Apr 02, 2015 10:45 pm, edited 1 time in total.

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banedon
 Post subject: Re: GAL Address Decoder
PostPosted: Thu Apr 02, 2015 9:57 pm 
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I've tried
Code:
FIELD AddressBus = [A15..4,0,0,0,0];

and
Code:
FIELD AddressBus = [A15..4,X,X,X,X];

But both give errors.

Thinking about it, I could simply chop the last 4 bits off of the values being tested. I.e.

Code:
TABLE AddressBus => Selects {
   ['H'000..'H'1FF] => 'b'100000; /* Non-swap RAM */
   ['H'200..'H'7FF] => 'b'010000; /* Swap RAM */
   ['H'800..'H'800] => 'b'000100; /* VIA 1 */
   ['H'801..'H'801] => 'b'000010; /* VIA 2 */
   ['H'900..'H'FFFF] => 'b'000001; /* ROM */
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banedon
 Post subject: Re: GAL Address Decoder
PostPosted: Thu Apr 02, 2015 10:01 pm 
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Nope that doesn't work. I'm thinking that A3 to A0 are assumed as having a value of 0...

[EDIT] Compiling the project and writing it to a 22V10B GAL shows that... it doesn't work. LOL.
I'll test it with my oscilloscope tomorrow to find out what the outputs are trying to do.
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BitWise
 Post subject: Re: GAL Address Decoder
PostPosted: Fri Apr 03, 2015 12:27 am 
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Posts: 996
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I couldn't get the FIELD definitions to work but it compiles correctly when done long hand
Code:
/* Inputs */

PIN 1      = PHI2;
PIN 2      = R_W;
PIN [3..6]      = [A15..12];
PIN [7..8]   = [A5..4];

/* Outputs */

PIN 14     = !RD;
PIN 15     = !WR;
 
PIN 16     = !VIA1;
PIN 17     = !VIA2;
PIN 18      = !SRAM;
PIN 19      = !BANK;
PIN 20      = !ROM;

/* Rules */

RD    = PHI2 &  R_W;
WR    = PHI2 & !R_W;

SRAM    = !A15 & !A14 & !A13 & !A12
   # !A15 & !A14 & !A13 &  A12;

BANK   = !A15 & !A14 &  A13 & !A12
   # !A15 & !A14 &  A13 &  A12
   # !A15 &  A14 & !A13 & !A12
   # !A15 &  A14 & !A13 &  A12
   # !A15 &  A14 &  A13 & !A12
   # !A15 &  A14 &  A13 &  A12;

VIA1   =  A15 & !A14 & !A13 & !A12 & !A5 & !A4;
VIA2   =  A15 & !A14 & !A13 & !A12 & !A5 &  A4;

ROM   =  A15 & !A14 & !A13 &  A12
   #  A15 & !A14 &  A13 & !A12
   #  A15 & !A14 &  A13 &  A12
   #  A15 &  A14 & !A13 & !A12
   #  A15 &  A14 & !A13 &  A12
   #  A15 &  A14 &  A13 & !A12
   #  A15 &  A14 &  A13 &  A12;

In the traces vectors 1-4 test RD and WR decoding, 5-20 test each 4K page from 0xxx to Fxxx, 21-22 test VIA1/2 and 23-24 test unmapped IO page addresses.


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BigDumbDinosaur
 Post subject: Re: GAL Address Decoder
PostPosted: Fri Apr 03, 2015 1:17 am 
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BitWise wrote:
I couldn't get the FIELD definitions to work but it compiles correctly when done long hand.

I've never been able to get FIELD statements to work in WinCUPL. I believe this is yet another of many bugs in that software.

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banedon
 Post subject: Re: GAL Address Decoder
PostPosted: Fri Apr 03, 2015 7:24 am 
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Thanks for advising as I may have wasted a lot more time on using FIELDs.
I know that WinCUPL is free software so I shouldn't complain, but you'd think that they'd fix such an obvious and important bug?
Unless perhaps it's device specific?

I was hoping to use the FIELD command to make things more readable and so easier to change in the future. However, it looks like I'll have to do it the manual way. :(


[EDIT] I've emailed Atmel to see what they say. Not sure it'll do any good, but they might be able to shed a little light.
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banedon
 Post subject: Re: GAL Address Decoder
PostPosted: Fri Apr 03, 2015 2:35 pm 
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I tried the following as a test. Also doesn't work.

Code:
Name     fieldtest ;
PartNo   g22v10b ;
Date     03/04/2015 ;
Revision 01 ;
Designer Engineer ;
Company  none ;
Assembly None ;
Location  ;
Device   g22v10 ;

Pin [2..3] = [Input0..1];

Pin [22..23] = [Output0..1];

Field inp = [Input0..1];
Field outp = [Output0..1];

TABLE inp => outp {
   0 => 1;
   1 => 3;
   2 => 0;
   3 => 2;
}
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BigEd
 Post subject: Re: GAL Address Decoder
PostPosted: Fri Apr 03, 2015 3:09 pm 
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When you say it doesn't work, do you get any kind of diagnostics or output?
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banedon
 Post subject: Re: GAL Address Decoder
PostPosted: Fri Apr 03, 2015 3:26 pm 
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BigEd wrote:
When you say it doesn't work, do you get any kind of diagnostics or output?

It just outputs 0.

[EDIT] just to expand on this: I got 0 on all pins. Tried a different GAL just to be sure.
(sorry - I was in a rush/middle of doing something and snapped off a quickly reply).


Last edited by banedon on Fri Apr 03, 2015 3:44 pm, edited 4 times in total.

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BigEd
 Post subject: Re: GAL Address Decoder
PostPosted: Fri Apr 03, 2015 3:30 pm 
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Hmm... not as helpful as it might be!
[In the sense that I've seen more helpful tools - instead of a syntax error, you get an explanation or even a hint.]


Last edited by BigEd on Fri Apr 03, 2015 4:51 pm, edited 2 times in total.

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banedon
 Post subject: Re: GAL Address Decoder
PostPosted: Fri Apr 03, 2015 3:40 pm 
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So far, so good. Thanks to bitwise I've gotten a better idea of how this works (thanks to his example from earlier). Modifying that, I've added in a couple of swap bank inputs and four swap bank chip select output.

One slight concern is that the high pins are outputting 4V-4.3V instead of 5V. Is this normal? With CMOS I though it outputs the same level as VDD (in this case 5V). I know CMOS is supposed to be 2/3rds of VDD so 3.3V so it should be fine - but it just makes me wonder why this happens and if it's normal for a GAL.

BTW, the sb0 & sb1 input pins (pins 10 &11) are for selecting the swapbank RAM. There are 4 possible value:
00 - bank 0 selected (SWAPBANK0 / pin 19)
01 - bank 1 selected (SWAPBANK0 / pin 20)
10 - bank 2 selected (SWAPBANK0 / pin 21)
11 - bank 3 selected (SWAPBANK0 / pin 22)

Code:
Name       AddressDecoder;
Partno     Lattice22V10B;
Date       02/04/15;
Revision   01;
Designer   shalewyn.com;
Company    shalewyn.com;
Assembly   XXXXX;
Location   XXXXX;
Device     g22v10;


/*
 * Lattice GAL 22V10B pinout, DIP, top view
 *
 * I/CLK.[ 1     24 ].VCC
 *   I.[ 2     23 ].I/O/Q
 *   I.[ 3     22 ].I/O/Q
 *   I.[ 4     21 ].I/O/Q
 *   I.[ 5     20 ].I/O/Q
 *   I.[ 6     19 ].I/O/Q
 *   I.[ 7     18 ].I/O/Q
 *   I.[ 8     17 ].I/O/Q
 *   I.[ 9     16 ].I/O/Q
 *   I.[ 10    15 ].I/O/Q
 *   I.[ 11    14 ].I/O/Q
 * GND.[ 12    13 ].I
 *
 *
 *
 * $1000-$1FFF   -   %0000 0000 0000 0000 - %0001 1111 1111 1111
 * $2000-$7FFF   -   %0010 0000 0000 0000 - %0111 1111 1111 1111
 * $8000-$800F   -   %1000 0000 0000 0000 - %1000 0000 0000 1111
 * $8010-$801F   -   %1000 0000 0001 0000 - %1000 0000 0001 1111
 * $8020-$802F   -   %1000 0000 0010 0000 - %1000 0000 0010 1111
 * $8040-$804F   -   %1000 0000 0100 0000 - %1000 0000 0100 1111
 * $9000-$FFFF   -   %1001 0000 0000 0000 - %1111 1111 1111 1111
 *
 *
 * !Pin 17 - non-swap RAM   $0000-$1FFF
 * !Pin 18 - Swap bank 0  - $2000-$7FFF
 * !Pin 19 - Swap bank 1  - $2000-$7FFF
 * !Pin 21 - /VIA 1       - $8000-$800F
 * !Pin 22 - /VIA 2       - $8010-$801F
 * !Pin 23 - /ROM         - $9000-$FFFF
 *
 *
 * Inputs
 */

/* Inputs */

PIN 1      = PHI2;
PIN 2      = R_W;
PIN [3..6] = [A15..12];
PIN [7..9] = [A6..4];
PIN 10     = sb0;
PIN 11     = sb1;

/* Outputs */

PIN 14     = !RD;
PIN 15     = !WR;
 
PIN 16     = !VIA1;
PIN 17     = !VIA2;
PIN 18     = !BASERAM;
PIN 19     = !SWAPBANK0;
PIN 20     = !SWAPBANK1;
PIN 21     = !SWAPBANK2;
PIN 22     = !SWAPBANK3;
PIN 23     = !ROM;

/* Rules */

RD    = PHI2 &  R_W;
WR    = PHI2 & !R_W;

BASERAM   =   !A15 & !A14 & !A13 & !A12;

SWAPBANK0   =   !A15 & !A14 &  A13 & !A12 & !sb0 & !sb1
       # !A15 & !A14 &  A13 &  A12 & !sb0 & !sb1
      # !A15 &  A14 & !A13 & !A12 & !sb0 & !sb1
      # !A15 &  A14 & !A13 &  A12 & !sb0 & !sb1
      # !A15 &  A14 &  A13 & !A12 & !sb0 & !sb1
      # !A15 &  A14 &  A13 &  A12 & !sb0 & !sb1;

SWAPBANK1   =   !A15 & !A14 &  A13 & !A12 & !sb0 & sb1
       # !A15 & !A14 &  A13 &  A12 & !sb0 & sb1
      # !A15 &  A14 & !A13 & !A12 & !sb0 & sb1
      # !A15 &  A14 & !A13 &  A12 & !sb0 & sb1
      # !A15 &  A14 &  A13 & !A12 & !sb0 & sb1
      # !A15 &  A14 &  A13 &  A12 & !sb0 & sb1;

SWAPBANK2   =   !A15 & !A14 &  A13 & !A12 & sb0 & !sb1
       # !A15 & !A14 &  A13 &  A12 & sb0 & !sb1
      # !A15 &  A14 & !A13 & !A12 & sb0 & !sb1
      # !A15 &  A14 & !A13 &  A12 & sb0 & !sb1
      # !A15 &  A14 &  A13 & !A12 & sb0 & !sb1
      # !A15 &  A14 &  A13 &  A12 & sb0 & !sb1;

SWAPBANK3   =   !A15 & !A14 &  A13 & !A12 & !sb0 & sb1
       # !A15 & !A14 &  A13 &  A12 & sb0 & sb1
      # !A15 &  A14 & !A13 & !A12 & sb0 & sb1
      # !A15 &  A14 & !A13 &  A12 & sb0 & sb1
      # !A15 &  A14 &  A13 & !A12 & sb0 & sb1
      # !A15 &  A14 &  A13 &  A12 & sb0 & sb1;

VIA1   =  A15 & !A14 & !A13 & !A12 & !A5 & !A4;
VIA2   =  A15 & !A14 & !A13 & !A12 & !A5 &  A4;

ROM   =  A15 & !A14 & !A13 &  A12
   #  A15 & !A14 &  A13 & !A12
   #  A15 & !A14 &  A13 &  A12
   #  A15 &  A14 & !A13 & !A12
   #  A15 &  A14 & !A13 &  A12
   #  A15 &  A14 &  A13 & !A12
   #  A15 &  A14 &  A13 &  A12;
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cbscpe
 Post subject: Re: GAL Address Decoder
PostPosted: Fri Apr 03, 2015 4:50 pm 
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Posts: 491
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Hi banedon,

Lattice GALs have rather TTL output levels than CMOS output levels. It's normal that Voh is about 0.9V less then VDD.

I also have some suggestions regarding your decoder. You now create many swap bank select signals. Do you really intend to have as many SRAM chips? Wouldn't it be easier to have one large SRAM and create address mapping that match the bank select inputs?

Also I think your terms are not correct if BASERAM is $0000 to $1FFF as in the description the term would be

Code:
BASERAM   =   !A15 & !A14 & !A13


and the code for the Swapbanks would be for e.g. Swapbank 0

Code:
SWAPBANK0   =   !A15 & !A14 &  A13  & !sb0 & !sb1
            #   !A15 &  A14         & !sb0 & !sb1


Also the VIAs have two select pins. When using CS1 you can select decode VIAs using only one output of the GAL. E.g. you could create a select that as asserted for $8000 to $803F. This signal would be connected to /CS2 of both VIAs. CS1 of the first VIA would be connected to A4 and CS1 of the second VIA is connected to A5. Addresses $8010 to $801F would address the first and $8020 to $802F address the second VIA, the only thing is that you should never access $8030 to $803F as this selects both VIAs.

cheers

Peter
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banedon
 Post subject: Re: GAL Address Decoder
PostPosted: Fri Apr 03, 2015 5:50 pm 
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cbscpe wrote:
Hi banedon,

Lattice GALs have rather TTL output levels than CMOS output levels. It's normal that Voh is about 0.9V less then VDD.

I also have some suggestions regarding your decoder. You now create many swap bank select signals. Do you really intend to have as many SRAM chips? Wouldn't it be easier to have one large SRAM and create address mapping that match the bank select inputs?

Also I think your terms are not correct if BASERAM is $0000 to $1FFF as in the description the term would be

Code:
BASERAM   =   !A15 & !A14 & !A13


and the code for the Swapbanks would be for e.g. Swapbank 0

Code:
SWAPBANK0   =   !A15 & !A14 &  A13  & !sb0 & !sb1
            #   !A15 &  A14         & !sb0 & !sb1


Also the VIAs have two select pins. When using CS1 you can select decode VIAs using only one output of the GAL. E.g. you could create a select that as asserted for $8000 to $803F. This signal would be connected to /CS2 of both VIAs. CS1 of the first VIA would be connected to A4 and CS1 of the second VIA is connected to A5. Addresses $8010 to $801F would address the first and $8020 to $802F address the second VIA, the only thing is that you should never access $8030 to $803F as this selects both VIAs.

cheers

Peter

Hi Peter

Thanks for your advice and suggestions.

I certainly could try that, although I really wanted to get the wretched decoder working as a test before I considered such things first (which it now does! :)).
I could put in a 1Mbit device and then split down possibly, although I was looking at possibly keeping it to 4 separate devices so it's modular - you put in what you need. But I suppose with the price of SRAM these days...

With regard to the VIA's that isn't a bad way of doing it and is pretty similar (in part) to the way Garth Wilson's primer is set up.
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banedon
 Post subject: Re: GAL Address Decoder
PostPosted: Fri Apr 03, 2015 6:41 pm 
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cbscpe wrote:
Code:
BASERAM   =   !A15 & !A14 & !A13



I forgot to mention that you are quite correct with regard to this. Many thanks :)
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cbscpe
 Post subject: Re: GAL Address Decoder
PostPosted: Fri Apr 03, 2015 6:58 pm 
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Hi banedon,

you can even get one step further in simplifying decoding. When using a 32kbyte (62256) or 128kbyte (628128) device and in case you only have RAM from $0000..$7FFF I normally just tie A15 to the /CE of the RAM. In case you don't use a Bank Switching it's a 32kbyte device in case of Bank Switching it's a 128kbyte. So the GAL creates no /CE for the RAM at all. Bank select then is done via the following equations, where R15 and R16 are the signals that connect to the 128kbyte SRAM address pins A15 and A16.
Code:
R15     =  !A15 & !A14 & A13 & sb0
        #  !A15 &  A14       & sb0

R16     =  !A15 & !A14 & A13 & sb1
        #  !A15 &  A14       & sb1

so the decoder does not change whether you have only 32kbyte RAM or 128kbyte Bank Switched RAM. That makes it easier to test the decoder. Thanks to JEDEC you only have one PIN (VCC of the 32kbyte SRAM) that needs a jumper or a different wire on a solderless breadboard. And as you said, a 128kbyte SRAM e.g. an AS6C1008-55 comes in PDIP has an access time of only 55ns, good for a 10MHz system is cheap, they sell currently for about 3USD.

As for bankswitching, sometimes you want to copy data from one bank to the other, therefore I would introduce 4 bankswitching signals, one set of 2 signals that control the bank you read from and 2 signals that control the bank you write to
Code:
R15     =  !A15 & !A14 & A13 & sb0r &  RW
        #  !A15 &  A14       & sb0r &  RW
        #  !A15 & !A14 & A13 & sb0w & !RW
        #  !A15 &  A14       & sb0w & !RW

R15     =  !A15 & !A14 & A13 & sb1r &  RW
        #  !A15 &  A14       & sb1r &  RW
        #  !A15 & !A14 & A13 & sb1w & !RW
        #  !A15 &  A14       & sb1w & !RW


without creating select signals for the RAM you have plenty of free pins on your GAL.

cheers

Peter
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6502.org is an ongoing project by Mike Naberezny and contributors.