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 Post subject: VIA Handshake Questions
PostPosted: Wed Mar 18, 2015 12:12 pm 
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Posts: 158
Trying to get more familiar with the VIA and came across this snippet (page 11) in the datasheet. The important part is in bold.

Quote:
Read Handshaking provides effective control of data transfers from a peripheral device to the
microprocessor. To accomplish the Read Handshake, the peripheral device generates a Data Ready signal
to the W65C22N that indicates valid data is present on PA or PB. In most cases, this Data Ready signal will
interrupt the microprocessor, which will then read the data and generate a Data Taken signal. Once the
peripheral senses the Data Taken signal, new data will be placed on the bus. This process continues until
the data transfer is complete.


I'm not sure if the bold is a typo or not, but... it's making me think about the handshake process.
From what I can gather, in handshaking mode, the following events occur:
  1. A read from PA after CA1 has been asserted will assert CA2.
  2. A write to PA or PB will assert CA2/CB2, until a peripheral device asserts CA1/CB1.
  3. The VIA doesn't actually know whether a read handshake or write handshake is occurring. It just sets/resets CA2 depending on whether a read or write to the PA register was received (using slightly-different timings for each). Likewise, an IRQ is generated solely based on when the peripheral asserts CA1 in either case. The only difference between the two handshakes is the order of events.
Is the above correct?

The above points make me wonder about two things:
  1. Is half-duplex bidirectional communications using solely port A and CA1/CA2 handshaking possible, provided there is a way for each end (not the VIA) to know whether the handshaking signals are in the "idle" position?
  2. Can PB be used for read transfers at the cost of the CA1/CA2 control lines (and a dummy read to PA after reading PB)? Normally, I don't think one would use ALL PB lines solely for interfacing to an 8-bit peripheral, as PB6/PB7 have special purposes. Perhaps a 4-bit port for Hitachi LCD drivers. But it does give PB read (write?) handshakes while ensuring the shift register is still available.


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PostPosted: Wed Mar 18, 2015 7:17 pm 
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Although I'm quite cozy with the VIA, the handshake operation is something I have not used. Read on though:

cr1901 wrote:
Trying to get more familiar with the VIA and came across this snippet (page 11) in the datasheet. The important part is in bold.

Quote:
Read Handshaking provides effective control of data transfers from a peripheral device to the
microprocessor. To accomplish the Read Handshake, the peripheral device generates a Data Ready signal
to the W65C22N that indicates valid data is present on PA or PB. In most cases, this Data Ready signal will
interrupt the microprocessor, which will then read the data and generate a Data Taken signal. Once the
peripheral senses the Data Taken signal, new data will be placed on the bus. This process continues until
the data transfer is complete.


I'm not sure if the bold is a typo or not

I don't see any problem with it.

Quote:
, but... it's making me think about the handshake process.
From what I can gather, in handshaking mode, the following events occur:
  1. A read from PA after CA1 has been asserted will assert CA2.
  2. A write to PA or PB will assert CA2/CB2, until a peripheral device asserts CA1/CB1.
  3. The VIA doesn't actually know whether a read handshake or write handshake is occurring. It just sets/resets CA2 depending on whether a read or write to the PA register was received (using slightly-different timings for each). Likewise, an IRQ is generated solely based on when the peripheral asserts CA1 in either case. The only difference between the two handshakes is the order of events.
Is the above correct?

It sounds like it.

Quote:
The above points make me wonder about two things:
  1. Is half-duplex bidirectional communications using solely port A and CA1/CA2 handshaking possible, provided there is a way for each end (not the VIA) to know whether the handshaking signals are in the "idle" position?
  2. Can PB be used for read transfers at the cost of the CA1/CA2 control lines (and a dummy read to PA after reading PB)? Normally, I don't think one would use ALL PB lines solely for interfacing to an 8-bit peripheral, as PB6/PB7 have special purposes. Perhaps a 4-bit port for Hitachi LCD drivers. But it does give PB read (write?) handshakes while ensuring the shift register is still available.

It looks like you could use PA for bidirectional communication. If I understand it correctly, you would not need to keep writing to the peripheral control register (PCR), only DDRA. Obviously the two ends would have to agree to a protocol so they don't both try to drive the line at the same time.

The PA and PB handshake modes are for things like printers, and actually my workbench computer's printer interface doesn't do it this way since I'm multiplexing so many things on one VIA (parallel printer, LCD, keypad, I²C port, beeper, RTC, serial port, ABORT button, and triggering my A/D converter). The diagram (unfortunately the least readable in my 6502 primer) is the first one at http://wilsonminesco.com/6502primer/IO_ICs.html. I tell about parallel printer interfaces in the circuit potpourri page of the 6502 primer at http://wilsonminesco.com/6502primer/potpourri.html#LPT, interfacing to the 4-bit LCD with the Hitachi controller you mention just above it at http://wilsonminesco.com/6502primer/potpourri.html#LCD (with driver code in multiple forms at http://wilsonminesco.com/6502primer/LCDcode.asm), and keypads just above that at http://wilsonminesco.com/6502primer/potpourri.html#KBD . The LCD does not have the signals to use the handshaking with CA1 & 2 or CB1 & 2.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?


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