Hi, I'm a new member...

I've been doing a little 6502 research, and have a few questions about PHI2. From what I understand, data transfers occur while PHI2 is high, so should PHI2 along with an address decoder be used to control the /CE (Chip Enable) pin on SRAMs, EEPROMs, and other memory chips? In some schematics I've seen PHI2 is used to control only /WE (Write Enable), while /CE is controlled by the address decoder. In others (which contain memory chips) PHI2 isn't used at all. How exactly should PHI2 be used?

Just don't let your system write to RAM unless phase 2 is high. I've seen people run into problems writing to unintended addresses when they didn't use phase 2. The problem is that depending on your glue logic, the selected RAM may get the signal to write before all the address bits have been valid and stable for the minimum set-up time, so you corrupt something you didn't mean to before doing the intended write. If there's any chance the address bits could start going invalid before the R/W is finished going up at the end of the cycle, there's another reason to gate the CS (or at least the WR\) with phase 2.

Don't gate the 6522's CS inputs with phase 2 though. It has its own phase-2 input and needs the CS pins valid a certain amount of time before phase 2 goes up. I'm sure this is true of other 65-family I/O ICs too, but I haven't gotten bit by doing it wrong on the other ones I've used (like the 6520 and 6551).

This information is repeated here from other posts, so use the search on the archives when possible.

Thanks Garth. Sorry about not using the search, I'll do so from now on.

In the WDC data sheet for W65C02S all timing is with reference to the PI2 INput. In the older designs the PHI2 OUTput was used as reference. Is there an actual design change that affects how the new processor shall be used?
I find no application notes on WDC homepage that can shred some light over this issue. Therefore I ask here if the peripherals PHI2 shall be connected to PHI2 out, or f.ex. two buffers from the clock source shall be used. One to supply the level critical PHI2 in and one for the rest of the system.

Doggone, you're right! I never noticed that. It definitely is an error, and I expect it crept in because of the 65816 which has no phase-2 output. It wouldn't be the first time someone found an error in their WDC's diagrams and spec.s. Which data sheet did you look at? On my older one, it has a delay of up to 40ns from phase-2 input to phase-2 output even for the 10MHz part, and then they reference everything to the input; but 40ns is almost as long as the clock is either high or low, so obviously that won't fly. I looked at a newer data sheet though, and it was fixed.

The phase-2 input and phase-1 output seem to be primarily intended for hanging a crystal or an RC right on the processor itself so an external oscillator is not always needed. It wouldn't make sense to connect the actual processor's innards to the phase-2 input since that one is a Schmitt-trigger input specifically so it can handle the slowly ramping voltage you'd get from a capacitor and resistor connected directly for using the onboard oscillator.

Hi Everyone,

If I may be so bold as to suggest that you email this question to WD.
Last year I emailed a minor typo in the data-sheet and they were very friendly in their response.

Cheers,

Paul

As I said above, I looked at a newer data sheet and they had already fixed it.

According the the 65c02 datasheet, R/W will be valid no later than after the address setup time has elapsed. However, the datasheet's timing diagrams don't actually show the R/W pin's timing; it is combined with the address timing.

In the preceding paragraph, am I correct in understanding that you are describing two different events?

1. After PHI2 transitions from hi-to-lo, there is a chance that R/W will become valid for the current bus cycle before the address bus does. This results not only in writing to the wrong addresses, but also writing garbage to the wrong addresses (setup time violation).
2. It is possible that R/W from the previous bus cycle stays valid longer than the address bus does after PHI2 transitions from hi-to-lo. Again, this writes the wrong addresses, but also potentially doesn't even write the value on the data bus (setup time violation).

I'm trying to use this article to help understand setup-time vs hold-time, but the hold-time part isn't making much sense (why is only W conducting- and not the output path to Q- during hold-time? EDIT: I guess it's supposed to be visualizing that the transmission gate on the input is closing, but the input must remain stable until the gate completely closes, otherwise the changing input will corrupt the value stored during setup time).

You could get into trouble on both sides. The times given for address and R/W\ are guaranteed maximums for after the fall of phase 2. They will normally be less than the maximums, and there's no implication that they will become valid at the same time, or that a particular one come first rather than last in the order. If one output is a little stronger than another, or has less capacitive load on it, it may rise or fall sooner than its neighbor. Since edges don't have infinitely high slew rates (at the processor pins, let alone further down the lines where there's stray inductance and capacitance), there may also be a problem with non-uniform thresholds at inputs, so one input may see a "1" sooner than another one connected to the same line, as the voltage rises. If there's ringing, it may need time to die out a bit before there's a final, dependable level on the line. Propagation delays through glue logic may also come into the picture. The RAM may have an address set-up time you have to get through before letting it write. There are just too many variables. You might disregard it all and get lucky and seem to get away with it initially, only to have it foul up later when it gets cold or hot, or the power supply voltage isn't quite the same, or there are small spikes from nearby static discharges, or suddenly new software uses addresses in memory that had been getting written to inadvertently but you just didn't know it yet, or... you get the picture.

_________________
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What's an additional VIA among friends, anyhow?

I take it one can assume all these effects also happen during reads too? I.e. the data bus has garbage on it while the address bus settles from the RAM/ROM/and non-6502 I/O chips being fed invalid addresses? I guess the logic here is that reads only change the state of the processor, but because the processor ignores all the "fun" effects until a guaranteed time has elapsed after PHI2's rising edge (access time), nothing bad happens.

To sum up in one sentence: Qualifying the CS signal for RAM/non-6502 I/O writes is just a way to achieve the same bus stability that RAM/ROM/IO reads are guaranteed to have- for chips ignorant of the 6502 bus timing.

Programming EPROMs in a 6502-system must be fun .

On reads, the processor only needs a certain minimum data setup time before the fall of phase 2. It's not referenced to the rise of phase 2, but to the fall. Before that, it doesn't matter what a memory or I/O device puts on the bus.

I've been qualifying the RAM's CS\ with phase 2; but if you have a RAM that's pretty slow compared to the bus, you may want to qualify only its WE\ with phase 2 so it can get a head start getting selected before the rise of phase 2. There are SRAMs down to something like 6 or 8ns even in DIP now though, so it doesn't have to be an issue.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I do not qualify any chip selects with Ø2, as it is unnecessary. As long as reads and writes are gated by Ø2 there is no risk of corruption. It's generally not considered good design practice to wait until Ø2 goes high to select devices. The selection should occur as soon as the address bus is valid. The /OE or /WE inputs brought low only when Ø2 goes high. Due to the prop time in the glue logic, /OE or /WE will always slightly lag Ø2.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

That makes sense- /CS will "prepare" the outputs, and /OE or /WE will simply enable the output for reading or writing respectively. So there's no real time penalty for driving /OE and /WE later than /CS.

Amusingly, for the address decoding section, Garth's primer shows a circuit where /OE and /CS are both qualified with PHI2, and a circuit where only /CS is qualified by PHI2, but doesn't show a circuit for the case where only /OE and RWB is gated by PHI2.

Gating only /OE doesn't work, b/c at least with the SRAM I have on hand, /OE's logic level doesn't matter if /WE is asserted.

That's correct. In some devices, the response time to the /CS input is longer than to the /OE or /WE inputs. By asserting /CS as soon as there is a valid address, you give the device time to prepare for access while Ø2 is still low.


That's not always the case. Most devices seem to follow that behavior but it's not guaranteed in all cases. I decided a long time ago to only assert /OE when in a read cycle, and only assert /WE in a write cycle.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

Just make sure the RAM cannot be written to when phase 2 is low.

There are lots of ways to work it; but much of my point there is to show that you can do the whole job with a single 14-pin IC, and that beginners tend to make it much too complicated. As for reliability, the first circuit there is what I've been using on the workbench for over 20 years with no problems, and what was in an aircraft intercom we produced and sold for about 14 years (shown on the same page) and it never failed, even at temperature extremes (-40 to +180 deg F). RAM is available in speeds much faster than you need for this kind of scheme at 5 or 10MHz, not to mention 1 or 2MHz. There is so much margin at the lower frequencies that it is pointless to talk about getting the extra time by selecting the RAM before phase 2 goes up. When you get into the higher frequencies, then yes, more attention is needed as the timing margins get thinner and thinner.


I'm sure there are SRAMs that need OE\ high to be able to write, but I have not run into one myself. All the ones I've seen will ignore OE\ when WR\ is low.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?