First some pics! If the board is fully functional, these will be the pics I add the the header post on this thread. Unfortunately, I head to work tomorrow so it'll probably be about a week of on-off testing.

The 300MHz check box should be darkened, as that 300MHz can oscillator is what's soldered underneath.

First a pic of the top of the board. Again, after soldering in the connectors I put the board into a heated isopropyl solution in an ultrasonic cleaner I purchased on Ebay way back. Nice and clean after about 5 minutes.

Then a pic of the bottom... You can see I've reached the limits of a 4-layer board with the blue 30AWG WW wire making less critical connections.
These connections are between:
The SPI FLASH PROM and FPGA
The 300MHz main clock signal to the FPGA
The Program button to FPGA.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

After about 5+ OS installs and random BSOD, the problem has been nailed down to my PC's SSD's.
I won't name the manufacturer as this thread isn't a manufacturer review, but I can say that I'll do some additional research before purchasing the next SSD. There are many complaints for the 3 I own. 2 have failed. I currently am running on the last one... I'll order a small <100GB HDD SATA drive in anticipation of this one's failing, which is probably going to be pretty soon.

So this is the BS I struggle with on the eve of my boards success. No problem!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Everything has been reinstalled. No progress lost, just a progress delay due to poor product. Pisses me off...

Bittersweet moment: ISE14.7 sees the FPGA and SPI FLASH PROM, like it did in PVBV2.h, and successfully programs either one, but no video output. Not even an out of range, which is not an encouraging sign.

I set up all the constraint info and the FPGA PLL for a 300MHz clock input from the onboard can oscillator to output pixel clocks @148.581MHz and an internal cpu clock at 1/2 speed.

I've limited time each night to dedicate. I'll have time tonight to desolder the 300MHz oscillator and solder in a known good 200 MHz one.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Instead I drag out the 'scope and check for any output from U9, the 300MHz can oscillator. I see no clock... Checking part # and pinouts.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Jeezus, I would've fired myself. This 300MHz can oscillator, part# FXO-LC726R-300, is a 2.5V part! I'll have to settle for 200MHz for now, as I'll dismount the 300MHz part and mount the proven 200MHz can oscillator.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

The FTDI FT230X seems functional. I downloaded FTProg from FTDI's website and it sees the chip through the USB connection in order to program the 4 user config pins. One nice thing about this IC compared to the MCP2200, is that it has it's own internal clock. The MCP2200 needed an external 12MHz clock, also the MCP2200 package is abit larger so I'll keep this FT230X in the design.

I'm currently still testing this board in regards to the SyncRAM's and the old 1080p Verilog project I've used for PVB1. The first objective is to get this project working on 1 SyncRAM, which has been completed, although the white pixels are abit reddish for some reason. Then modify pin location constraints in the .ucf file for the FPGA, and get the project to work identically using SyncRAM #2, which has almost been completed. I'm seeing a skewing of video data, like an address line is incorrect. In searching for the problem, I've found another major flaw in regards to a data pin I/O that was unintentionally grounded. I've tried to lift the pin off the board and cut a trace in order to route it to it's destination without the ground via, but unfortunately the observed behavior is the same. I think either the FPGA and/or the SyncRAM is damaged as I've tried to touch up the solder around SyncRAM #2 more than 3 times with no change in behavior.

This will require another board run. I'll use fresh IC's, as I think heat may have slightly damaged the videoDAC/SyncRAMs during the hot air desoldering process.
These IC's are 8 weeks out, and I probably won't be able to order them till next week, so I'm taking abit of a rest now.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I'm starting to think it's not heat damage but rather maybe some SyncRAM address pins shorting together under the FPGA.
I need to have these boards made by another house that has the ability to 'tent' the vias, i.e. soldermask over the via. EPCB can't do this and I think I just got lucky with the earlier experiments.
I really didn't want to go through this learning curve of learning new PCB layout software, but I also can't afford to waste $200 on another run of boards that is likely to fail, so I'm going to have to dive in, now which software to use? I'll have to investigate... See you back here after the first board run from the new house.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

After learning KiCAD for a 6 layer board layout, PVBV2 is EOL. The reasons for this are:

The cost is rather high for a 6 layer board, so I decided to 'aim high' and maximize usage of all new knowledge including BGA mounting.

Currently focusing on a new design, called PVBV4, with a XC6SLX150-FG676C and 4x 400MHz 2Mx18 SyncRAMs.

Also, the 96 pin connector is done. After some research on high density connectors, I've realized the option is available for a 120 pin connector, but the board will have to be expanded to 4.5" horizontally which is not a problem. This will allow for a few things, including a 16-bit data bus and 8bpp color mapping from the 565 SyncRAMs but I will have to also redesign the mainboard backplane board.

A new thread will be started, hopefully soon.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Not a problem because you're freed from Express PCB's limitations, is that right?

Sounds like you're up and running with KiCAD! Any further comments on the switch to new software?

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

That may be true. But I should have said that since 2 more SyncRAMs are being added to the design, it's adding slightly more than 1" horizontally to the board dimensions. So for this new board design there will be 2 SyncRAMs, like the pic at the top of this page. The FPGA will be rotated 45degrees. The other 2 SyncRAMs will be to the right of the FPGA.
So with this fact, I was happy to find some cheap high pin-count male/female mating connectors after searching for at least an hour. The 120-pin connector is identical to the 96-pin connector currently in use, just 1" longer. In addition to the 120-pin connector there is also a 150-pin 3-row connector if that is needed.


Yes, up and running. Very exciting! With some confidence in BGA mounting and the ability to have a 6 layer board manufactured, my madness can be realized!

It took about 2 weeks to learn the flow. In addition to ME being slow and hard headed, I needed to do a board layout without schematics. This seems to be a foreign concept to most people using KiCAD.
There were some on the #kicad channel on irc.freenode.net that tried to point me in the right direction. They're a great help, great community in there, IC footprints, advice, etc.

In the end all I did was to start with a hierarchical schematic with 4 sheets. Within Sheet 1 was the FPGA, with power(s)/ground pins only. Sheet 2 contained other ICs with the powers/grounds connected to their NETs. Sheet 3 contained all connectors in the same manner. Sheet 4 was the power supply connector and origin of the power/ground NETs.

Did I mention KiCAD lets one rotate a PCB footprint by 'x.0' degrees?

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Yes, and that's a pity. Certainly there are solid reasons why the schematic approach serves some people well, but others prefer no schematic (or at least none that's readable by the PCB software). And Express PCB wins adherents by supporting that option, whereas the KiCAD tutorial neglects it (so far).

Having made the switch from EPCB to KiCAD, are there any tips you can offer, EE, to others embarking on the change? (You could even start a new topic.)

Is this the absolute minimum, then? (Seems like you've partially adopted the schematic approach; nothing wrong with that.) And would these files be useful as a template for other users, to be edited into a different project altogether? And would you be willing to share the files?

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

The only advice I have is to use the IRC channel for some pretty quick advice (no matter how foolish the question may seem), also post questions to the forum on the http://www.kicad.info website. Also, check out the videos by Chris Gammel of Contextual Electronics on youtube. There's links to them (CE Videos) from the http://www.kicad.info site as well.


I'm not sure if it is the absolute minimum, but it is my first successful starting point. However, I have recently learned how to manually assign a NET to a pin of a footprint. I'll have to experiment with this tonight.


I'd be willing to share all the project files from the first apparent success of a design for PVBV2 that was 90% complete. I'm not sure there's enough info to warrant a new thread though...

EDIT: BTW, I currently use the latest stable release version BZR 5376 available from the official site.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

After a little more experimentation, I believe the absolute minimum schematic required is one that represents the power(s)/ground(s) NETs, no need to include bypass cap's. In my case, there is a ferrite bead connecting VEE(3.3vin) to VCC(3.3vreg). I included the ferrite bead in the schematic in the form of an inductor, since it defines VCC with a footprint of an 0603 SMD cap.

Attempting to assign a NET on any pin in a brand new PCB layout, without this most basic schematic, gives an error: 'unrecognized NET'.

I need to reinstall my screen capture utility, and I can start uploading some pics.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Without the need to create any special symbols for FPGA's or any other IC's in Eeschema (the schematic editor portion of KiCAD), one can save ALOT of time. The barrel jack connector may not even be needed, but these are the NETs Eeschema passes on to PCBnew for the power planes. Although in my project VEE is not a plane, it's a filled copper pour.
Through some experimentation, I discovered this is all I needed to do in Eeschema for a rather complex FPGA design and can add bypass cap's later in PCBnew (PCB layout editor). Also, any pin can be manually assigned to one of these: VCC, VDD, VEE, GND.
So...
VEE is unfiltered 3.3VDC.
Power planes:
VCC is filtered 3.3VDC.
VDD is filtered 1.2VDC after the VReg.
GND is GND.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I was able to reduce the schematic to a minimum. The barrel jack connector was not needed.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502