I want to use a PHI2 phase-based bus master scheme to allow two bus masters to access the memory subsystem in one cycle. The idea is to allow the CPU to have the bus lines when PHI2 is HIGH by wiring the BUS ENABLE input of the W65c02 to PHI2. Is this a good idea?

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The Apple II did a similar thing with external buffers (before the 6502 had a BE pin) so the processor and the video could both access the same memory at the same time at full speed with no conflicts. Hence the odd clock speed of 1.07MHz (or whatever it was).

While I can think of things about the idea that I don't have the answers to, I do want to point out that the 6522's won't work if the address and CS pins are not valid a certain amount of time before phase 2 goes up. One way around it, if your clock speed is slow enough to give you the extra timing headroom for any VIAs you might want to use, is to delay the phase-2 rising edge to the I/O without delaying the falling edge. That way the VIAs will have time to get valid and stable address and CS lines before phase 2 rises. You just have to make sure the VIA is fast enough to be able to work with the amount of its modified phase-2-high time left, since the resulting duty cycle may only be around 30%.

Otherwise it might be best to use a different method so each processor has its own I/O even though the two share the same memory. Then only the memory would be shared (and through external buffers), while the I/O could work the normal way.

This project uses no VIAs. My main concern about the idea was the fact that while PHI2 is transitioning, the address decode logic will be fed invalid data since neither bus master will have settled. Is this silly to worry about?

_________________
Thanks for playing.
-- Lord Steve

Another thing just occurred to me-- You'll need to make sure you can't write to unintended RAM addresses. There is a chance that, depending on timings, the RAM (or anythng else you write to) may get the selects and R/W\-low to go ahead and write before all the address lines feeding it have been valid and stable for the minimum set-up time the particular chip requires.

> Is this silly to worry about?

Definitely not. The job can be done, but it'll only be luck if you get it going without poring over the chip manufacturers' timing diagrams and charts and working things out by the worst-case numbers that are applicable to the range of operating temperatures, bus capacitances, and power supply voltages you expect to encounter with your creation.

The SRAM chip I am using has a Address setup time of ZERO ns before /WE goes low, starting the write cycle.

But, after looking at the timing diagrams, the problem will seem to be bus contention immediately after PHI2 transitions. PHI2 controls which master has the bus: HIGH being the 65c02 and low being a 25 ns GAL22V10. The datasheet specifies a minimum address hold time of 10 ns after PHI2 falls. The GAL22V10 datasheet specifies a minimum time for INPUT to OUTPUT ENABLED of 3 ns. So, the CPU could be clinging on for dear life to the bus, while the GAL is smashing the heel of its boot on the 6502's knuckles. The resulting garbage on the address bus could tell the decoder to select SRAM and if the CPU was just WRITING (/WE low) then SRAM could be corrupted and my day ruined.

Am I right? What are some solutions? The system clock will run at 6.5MHz. I could use a 25 MHz clock to create a quadrature clock and use the first quarter of each phase as a settling time for the signals. The logic would shut off the appropriate bus and then "clock" the address decoding logic. Is that overkill?

_________________
Thanks for playing.
-- Lord Steve

Anybody?

_________________
Thanks for playing.
-- Lord Steve