Hi guys

I'm reading bits and pieces of WDC 65C816/65C02 manual. Towards the back there is a section for the Rockwell 65C02 which mentions the RMB, SMB, BBS and BBR instructions.
The impression I get is that these are solely implemented on Rockwell's R65C02 and not on the WDC W65C02. However, I'm sure I've seen people mentioning these instructions in relation to WDC.
Can anyone confirm if they are just for the WDC 65C02? And if so, do they clash with WDC instructions (opcode-wise)? BTW I know that they are incompatible with the 65C802 and 65C816.
I'd like to know as I'm thinking of including the above in my assembler if possible.

I can answer this myself. Looking at the list of WDC instructions it seems that the above instructions clash.
For example: BBR5 is $5F. WDC $5F is EOR Absolute Long Indexed, X

Oh well.

WDC's 65c02 does have the SMB, RMB, BBS, and BBR instructions, as of the mid-1990's or so. The '816 uses those op codes for other instructions; but some of the documentation is still mixed, giving the 816's table in the '02 data sheet. (Documentation does not seem to be WDC's greatest area of strength. Not by a long shot.)

These instructions are apparently of most value in microcontrollers where I/O is in ZP. I/O is where those instructions would have the most value, but it takes a lot of levels of logic, and therefore a lot of gate delays, to do such fine-grained address decoding in our home-brew projects, unless you use programmable logic. I've never used them myself.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thanks Garth. I obviously got confused somehow between the 65C816 and 65C02 instruction sets.
I'm glad to have been proved wrong as the above instructions look quite useful which is why I'd like to include them. I'm slowly going through the 65C816/65C02 manual and it's proving to be as good as you promised in your primer.

Take a look also at TRB & TSB. These are on both the WDC 65c02 and 65816 and operate in zero page and absolute addressing.

Load the bits you want set or cleared in A then call TRB or TSB with the IO in the operand. They do the ORA or AND operation. For TRB, you don't have to invert value in A.

I use these in my IO code to manipulate bits.

Daryl

_________________
Please visit my website -> https://sbc.rictor.org/

Many peripherals have two or more chip select inputs. How about using a couple of '688s or similar to match for the address range? Prop times around 14 ns for the HC version, apparently. You then need another gate or two to prevent RAM from kicking in when you don't want it to, but it's a start.

Let's go one step further: The '688 can check nine bits at once, provided that one of the bits is low, by using the output enable as an extra bit. That's enough to tag out a half-page chunk of space. Add a NAND with an inverted A15 and you have an active-low RAM CS that selects the low 32k of address space except for half a page which is used for I/O, in two gate delays. Your 6522 has four register selects, so it needs A0-A3 for that, and A7-A15 are used to qualify one of the chip selects, leaving A4-A6 and one active-high chip select to work with... And a "free" gate delay to decode with. If you're feeling cheap, wire it directly, if you're feeling extravigant toss something like a '138 in there (but not a '138 itself, as it has active-low outputs and the only available CS is active-high). Or pick a different comparator...

So, that's I/O mapped to ZPage in two gate delays using discrete logic. Good enough?

Also note that TRB and TSB actually perform two distinct operations. The T in these mnemonics means "test." Not only are bits twiddled according to the mask in the accumulator, a separate Boolean operation that is analogous to a BIT # instruction is performed on the affected location before the bits are flipped. That tells you whether the bits on the targeted location were already in the desired state, or not.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

I've been writing 65xx assembly language programs for decades, mostly for the 65C02 since the mid-1980s. I have never found those instructions to be of use and in fact, when I developed a 65C02 machine language monitor for the old Fiscal Information Uni-FI terminal server boards (65C02 powered), I didn't even bother to include BBR, BBS, RMB and SMB in the mnemonic table. WDC did, in my opinion, the right thing when they preempted those opcodes for the 24 bit addressing instructions in the 65C816.

RMB and SMB, in particular, are very limited in their usefulness, as they can only be used on zero page locations. Unless a running program intends to store all bit field data on zero page, it will have to resort to using AND, OR, TRB and TSB to twiddle bits.

As for putting the I/O block in zero page so as to take advantage of RMB and SMB, that tends to create some significant glue logic challenges, not the least of which is that the gate delays incurred in such fine-grained decoding will quickly add up. Performance that might be gained by decoding the I/O block to zero page may be offset by the lower maximum Ø2 rate that can be attained. I personally would not do it, both because of the glue logic required and because zero page (with the 65C02, at least) is too valuable for other purposes (e.g., Forth's data stack).

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

The 74HC521 is the same thing. Unfortunately the maximum delay, ie, the one you have to design around, is 40ns, twice that of a a '00; so we can't call it one gate delay just because it's one trip through the IC. The 74ACT521 is much better at 12ns max, about the same as 74F521. 74ABT is faster, but alas, I have not been able to find a 74ABT688 or '521 available. If you find a source, please, please let me know before it goes away! DIP or SO is fine.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I think we're in agreement that there's a tradeoff involved, so let's look at specifics and become educated rather than adhering to any previous stance.

I'm on board, nyef. As for two gate (package?) delays, that can be a matter of 7.5 ns, maximum. The '688 you mention is a great starting point, especially since IDT makes one, the 74FCT521C, which is listed at 4.5 ns, max. ('688 and '521 are the same.) As for adding more inputs, it's hard to beat the 74LVC1G332. This is a 3-input AND in a tiny package. One of those would give you two extra address inputs; two would get you four extra, and so on. (Each 3-AND would feed an input of the '688.) The delay for the '1G332 is 3 ns max. You could make a 27-input circuit and the total delay would still be only 7.5 ns max. This is not a delay likely to force a reduction in system clock rate.

Maybe not but the FCT version I mentioned is available.

All my 6502 machines have had IO in zero-page, and all had a Forth stack there too, yet I had gobs of room left over. Yes I know YMMV, since no tradeoff is valid for all circumstances. I'm just flag-waving over the success-story side of things! RMB, SMB, BBS, BBR aren't good for much in general terms, but they totally rock for IO! See the thread major speedup with 65C02 I/O mapped into zero-page

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

The 74AC521 is faster than the 74ACT521, as seems to be the case with most of the 74AC vs. 74ACT devices.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

You're right. I checked my National Semiconductor data book and looked at the 3.3V Vcc for the AC which made it look a tad slower than ACT (which is only for 5V). In AC, it was indeed slightly faster than ACT. Checking again though, I see I did not make that mistake when I quoted the 'HC521 number.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

The Assembler could have a command line switch or an assembler directive to define the target CPU.

_________________
6502 sources on GitHub: https://github.com/Klaus2m5

Yes, that's the typical approach. The only other things to decide are if you are going to require one or have a default, and whether once a particular CPU is specified you will allow it to be changed later in the assembly.