While I wait until pay day (
) so that I can purchase a GAL/PAL programmer, I've put the following together. It represents what I have in mind for expansion. If you have some time and patience (or are bored enough
) please feel free to take a look.
NOTES:Memory$0000 to $1FFF .. 8KB .. non-swap RAM
$2000 to $7FFF .. 24KB .. swap RAM
$8000 to $9FFF .. 8KB .. I/O space
$A000 to $FFFF .. 24KB .. ROM
The address decoding is done by IC4 (a 74
AC138) which splits the map into 8KB segments. I've used AND gates to merge the '138s Y1,Y2,Y3 together and Y5,Y6,Y7 together.
Swap RAM is a memory area which can be swapped around within the 128KB SRAM IC (U3 - yep, I'll retag this later
). This is controlled by bit 7 of Latch 1 (IC5) which is attached to VIA #2 (IC3). This line is linked directly to bit 16 of the 128KB SRAM, making the 65C02 memory area $2000-$7FFF mapped to either $02000-$07FFF (bit7=low) or $12000-$17FFF (bit7=high). This should give 8KB + 24KB+24KB = 56KB of RAM but also allow the I/O space and 24KB ROM. The reason why the first 8KB ($0000-$1FFF) is not included is to avoid swapping out zero page and the stack (will cause issues+crashes). It also would store any user code which requests the swap - otherwise such code would swap itself out(!).
The above arrangement may well (and probably will) be replaced with a GAL to hopefully make things faster & simpler.IC9A truth tableA = line from IC4 Y0 (non swap RAM select, 0=selected, 1=deselected), B = swap RAM line (0=low RAM area used, 1=high RAM area used)
A B Output0 0 1 (A16=high, high RAM area selected)
0 1 1 (A16=high, high RAM area selected)
0 1 1 (A16=high, high RAM area selected)
1 1 0 (A16=low, low RAM area selected)
It doesn't matter if swap RAM is initially in the high or low part of the 128KB SRAM - as long as it stays consistent. By default it will be in the high area. if I used an AND instead of NAND here it will be the reverse.
VIAI've got a concern that the VIA's will be addressed too quickly and that they need some delay included to slow there selection down. Got to look into this.
KeyboardInitially, I'll have a numeric keypad hooked up to an AVR which does the scanning and interrupts the CPU when a key is pressed. This will eventually be replaced with a PS2 keyboard connection
LatchesTwo addressable latches are provided. Only one is used and of that only bit 7 which controls memory swapping. The rest are provided for future peripheral or memory control. Ordinarily I would have just left the one latch on there, but as I can control two with one VIA port - why not put in two? I supposed I could add something else instead of the second one...
All logic is CMOS AC where possible (for speed), although I might swap to HC if I get too much ringing, although hopefully that wont be needed as I'll be wire wrapping this project. The reset & power circuitry is not included (will use a DS1813+ and an LM7805 as usual).
Well, that's about it for now. Things will probably change as I discover things I mucked up no-doubt(!).
[EDIT] corrected a few bits