Hi guys

This is what I've got in mind for an extended RAM/ROM system for future designs.
The 65C22 port B is used to set two latches which can be used to:
1) select different RAM or ROM banks depending on 1 bit of one of the latches (so bank switching). See the line coming out of IC1 (Q0) in my diagram for an example.
2) select different regions of a RAM module if the module greater than the mapped area. See the line coming out of IC3 (Q0) in my diagram.

I can't see this not working, but as I don't have the parts (yet ) I cannot test this. Should be ok though.

Although the OS could keep track of values in zero page or something, I might see if I can find a way of reading the latch values back. I'm hoping to do this using the same VIA port (B), but not sure how to accomplish this yet. Possibly with a bidirectional buffer between the VIA port B and the latch input lines and one for each of the latch output lines (Q0 to Q7) for each latch. I could then use CB1 along with an inverter to control the direction? Food for thought!

I think you will be interested in the recent topic at viewtopic.php?f=1&t=3143.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thanks Garth. This doesn't quite run along the same lines (from what I can see) as I don't intend to swap to the 65C816 (yet) and don't plan to use an EEPROM to control address lines. I was thinking that using the above system I could swap between RAM banks, one or more of which could include a memory controller/battery backup and so be used as a form of fast storage. I would keep the bottom most section of RAM constant. Something like this:

or perhaps

For example purposes, consider a 128K SRAM with the lowest 64K mapped into 6502 address space. You'd like the ability to map the remaining 64K of RAM, one of four 16K chunks at a time, into address space at $8000..$BFFF. It seems to me that this would require controlling the A16, A15, and A14 address lines on the RAM and a mechanism or method for changing those lines only during an access into the 'banked' $8000..$BFFF address space.


While this type of memory management capability would be relatively simple to implement in the "soft decoder" portion of the PIC Loader/Decoder IC used in my small 65C02 systems, I'm not sure how you might implement this same capability in hardware. I suppose you could use a small EPROM as a decoder with CPU.A15, CPU.A14, and 3 bits from your VIA as inputs on the EPROM address lines along with five 4-byte tables inside the EPROM. Three bits in each byte would be used to drive the SRAM A16, A15, and A14 lines on a cycle-per-cycle basis with accesses to the $8000..$BFFF address space, where CPU.A15 = 1 and CPU.A14 = 0, producing either '010', '100', '101', '110', or '111' on those SRAM address lines, depending on the value of the three bits from your VIA. Of course, the remaining five bits of each byte could be used for "chip selects". In this case you might want to expand the size of the EPROM decoder tables to 256 bytes each using CPU A15..A8 plus 3 VIA bits as EPROM address inputs in order to produce "chip select" resolution down to a single page.

More later... Cheerful regards, Mike

Hi Michael

I hadn't considered using a microcontroller as a decoder. Not a bad idea at all for this kind of set up.

Can I ask a few questions with regard to yours?
- Does yours run a loop which constantly scans A13-A15 and change the chip selects as required? Or does it rely on interrupts?
- Also, which pic and at what speeds do you run it and your 6502?
- Finally, are there any major pitfalls/gotchas?

Many thanks

Sorry I missed your post!

My PIC based soft-decoder runs in a loop synchronized to a 1-usec (1-MHz) 6502 clock cycle. During each clock cycle the PIC uses the eight 6502 A8 through A15 address lines as inputs (index) into a 256 byte "decoder map" table which contains the chip select pin patterns for each page in 6502 address space. The PIC chip select output pins are updated approximately 187.5-nsecs before the rising edge of the PHI0 clock signal during each cycle.

I use a 40-pin PIC18F46K22 for "reset/loader/decoder + PIC I/O (serial + spi)" functionality or a 28-pin PIC18F26K22 for "reset/loader/decoder" functionality. The PICs run at 64-MHz (Tcy = 62.5-nsecs) which is roughly the same performance level as an AVR running at 16-MHz.

The biggest caveat is that the PICs I'm using aren't fast enough to provide a faster PHI0 clock while running the "soft decoder" function. This is fine for now since I'm interested in 'classic' 1-MHz systems.

Cheerful regards, Mike