BigDumbDinosaur wrote:
Thirty bytes would require at least 240 latches. I don't know if the 1508 can support that many. The only way to found out is to write minimal code that creates the required latches and I/O statements, and try simulating it in WinCUPL.
Thanks for the datasheet, BDD. And, as you say, writing some test code may be a useful step. PLDs are very general in their scope of application, and it can be hard to make the leap from what the datasheet says to a specific usage one might have in mind.
It's true a ROM will consume significant CPLD resources, but your "240 latches" estimate is misguided as no actual latches are required. A ROM's output is combinatorial -- determined entirely by currently prevailing inputs, and not dependent on any
stored information (as might be contained in a latch).
I'm no expert on ATF1508 but luckily that's not necessary to describe, logically, what a ROM does. A good place to start is to imagine a ROM that's one bit wide, not eight. The equation will be a Sum of Products -- ie; it describes an OR gate each of whose inputs comes from an AND gate. For every ROM location we want to contain a "0" we do nothing. For every ROM location we want to contain a "1" we include a Product Term (an AND gate) that says, "Hey! -- right now all the address inputs match
my address!" The Product Terms get summed (ORed) to produce the result.
Sorry I don't know the WinCUPL syntax. But a byte-wide ROM can be described by eight instances of such a Sum-of-Products equation. In a practical case you'll also need a Chip-Select input to control the tri-state outputs.
cheers, & HTH
Jeff
Attachment:
ROM logic .gif [ 3.74 KiB | Viewed 2853 times ]
PS- here's a one-bit wide ROM with 8 locations, addressed by A2, A1 and A0. In this example locations 0, 1, 4 and 7 contain ones; the remaining locations contain zero.
_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html