If you use Express PCB for board manufacture, please send an email to EPCB support if an exposed via ring is unnecessary in your design...

In most PCB design circles, an exposed via ring is undesirable, especially where a BGA IC is concerned.

I sent EPCB support an email today and got an immediate response regarding this issue and it's been forwarded...

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

You said you received a response. What did they say?

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

"...My request has been forwarded to the development team".

It would be great if they could make it so the software could make a via tented or untented. Otherwise, I think the default should be a tented via, not untented as it is now. What do you think?

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Tented seem much more useful to me. I can't see why you'd want you're vias uncovered?

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8 bit fun and games: https://www.aslak.net/

On occasion, I have used via as places to solder in blue wire when doing hardware patches. The default should be for via to be exposed, with the option to solder mask them if desired, as you would want under a BGA package.

I'd be surprised if EPCB actually did this. Some time ago I request the ability to put holes in the board that would not be through-plated and ringed. It never went anywhere.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

It's called "secondary drilling," as they take the board back to drilling after the thru-plating, so it adds expense. I have six such holes on the memory module (for the bypass capacitors embedded inside the board), and I chose to drill them out myself by hand. I should have just paid the extra, to save my time and get a cleaner hole. They are drilled, so getting them centered on the pad is not a problem, but they're thru-plated, and I drill out the thru-plating. As for the "ringed" part, just specify a pad that's smaller than the hole. I keep hearing about more and more of EPCB's limitations though.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I'm not nearly as experienced as you guys. But it seems to me that "closed" solutions, when there are "open" alternatives, are not a good thing. The advantages of the "closed" option needs to be compelling, or else there are literally no alternatives (programmable logic vendor software comes to mind). I use gEDA "pcb" currently. It has large flaws. But it does at least generate standard files.

ElEctric_EyE, does this mean you've given up with KICAD?

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8 bit fun and games: https://www.aslak.net/

I've not given up, because as BDD has pointed out my suggestion will likely go nowhere as his suggestion did. So my 4 year relationship with EPCB is likely done.
Anyway, I've had a desire to move onto 4+ layer designs. Using BGA's, with 256+ pads, in designs with tight real estate need 6 layers or more to route all of the pins out for use.

In KiCAD drawing a schematic in order to route all these pins seems a waste of time. Together with onboard memory devices, with no doubt wide data and address paths, this task is even more laborious...

From the experimentation I've done so far, I believe if one creates a schematic for the power section and the all GND/POWERs of each IC present in the design, then choose the footprints for each of the devices, then one could possibly route all the remaining signals manually.

I'm going on IRC to ask this question tonight and see if it's viable as the netlist will not be complete for the footprints, this may not work. These people are getting tired of me after just 2 days, I hear complaints in there Maybe they'll tolerate one more night of me!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502