Be sure you've gone through the sticky topic "Techniques for reliable high-speed digital circuits." See also my 6502 primer which has 22 chapters detailing different aspects of making your own 6502 computer, mostly hardware but a little software too, plus things like steps for a successful project, and workbench equipment.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Hi Jeff. Welcome to the group.

May I ask if you've considered using a single SRAM chip (64K or 128K) instead of a pair of 32K chips? The 64K and 128K chips I've seen have an additional active high chip select input that might be handy for address decoding. For example, you could use a single active low I/O chip select output ($8000..$BFFF) to drive active low I/O chip select pins as well as the active high RAM chip select pin ($0000-$7FFF + $C000-$FFFF).

Good luck on your project.

Cheerful regards, Mike

That for taking the time to print it out and take a look! If you are ever in Portland, OR, beer on me.
On the pull-ups, indeed those would be high in a wired-or/open collector setup. In my layout, the NMI, RDY, and IRQ (edit: IRQ was, NMI now is!) are all driven directly by the PIC, and I'll configure the PIC to always drive them (no tristate), so in theory no pull-up needed. I will leave the pull-ups in the schematic (and the board layout) in case I change something later. I will also edit the schematic to change them to 3.3K, as if I did do an open collector setup you are spot on that 10k is too high.

SOB: Yes.. great catch.. I was going to run through all of the 'disconnected' pin, so I'll add the pull-up to that one.

SRAM: Yea... The 65C02 could write to the SRAM where the rom is. I'll add a jumper pad for that, so if I later want to allow that it would be easy to do.

Interesting comment on the serial port.. I can see that with a 65C02 running a serial port that the hardware handshaking would be needed, as it would be easy to overflow the CPUs ability to handle input. In my case I am having the serial terminate inside the PIC, and I am implemented a large buffer that can hold data while being sent to the 65C02. In my experience using PICs and AVRs, I have not had any problem without handshaking as long as there is a good amount of buffer space. Since I have two SPI ports exposed, I hope to add a real keyboard and display so I don't need to use serial as the primary IO. Good input non the less.

Cheers!

Jeff

Yea.. I was surprised when I looked on the selector on digikey that most of the SRAMs were 32K or 128K... not many 64k chips. Using a single chip would simplify the board design as well. On the other hand I have a tube of 20 of the 32K SRAMS sitting here on my desk.. so there is that!

This has been a fun project in part because when I was in college (almost 20 years ago) I implemented a partial 6502 in VHDL and built up a board using the very early Xilinx FPGAs. It is fun to play with the technology of my youth! While I was an engineer at Intel I built a few 8086 boards, and strangely enough a TMS320C30 one, so getting back into good old PCBs in awesome.

Cheers,
Jeff

OH.. and I did a quick board layout to see how things fit. This is almost entirely auto routed, 4 layers (two signal layers, GND plane, Vcc plane). I'll tweak a few placements and make some small route optimizations and get this thing built!

Are you sure you can get a board made with the traces that close together?

By the way, it looks like you should have plenty of space to put those SRAM chips in parallel with the 65C02 which should make the routing much easier. It's usually possible to route the address bus and data bus from the 6502 to an SRAM chip with just a few via's (you may have to swap a few address bus and data bus lines on the SRAM). For example, check out the (manual, 2-layer, 50-mil grid) routing on my project:





===Jac