Delay routines, eh?
Reminds me of the Diablo daisy-wheel printers I reverse-engineered years ago. A fascinating design -- it was amazing how much was achieved using so little! I'm talking about
4 axes of simultaneous motion controlled in real-time by a primitive,
discrete-TTL CPU that had
no counter/timer and
no interrupts.
The loop (simplified substantially) ran something like this:
- if necessary, update the print-wheel servo
- if necessary, update the carriage servo
- if necessary, issue a pulse to the ribbon-advance stepper motor
- if necessary, issue a pulse to the paper-advance stepper motor
- (repeat)
The missing ingredient is regularity. To properly regulate mechanical motion the updates need to be issued at predictable intervals! That won't happen if the loop is free-running (allowed to iterate continuously). The execution time is too widely variable.
One solution would be to rewrite the code for constant execution speed. Take, for example, the test for whether a print-wheel update is required. You either go do the update or go do a delay of equal duration. Same for all the other tasks in the loop -- either do them, or instead do an equivalent delay. In fact the code is full of conditional branches -- far more so than the summary suggests.
Such a scheme might work alright, but no way was there room for all those delay loops! Did I mention the program memory only held 512 instructions?
What they did was reserve one of their
32 bytes of RAM (!) as a sort of accumulator for delay. According to the result of significant conditional branches, the delay byte would have various values added to it -- and the resulting delay was postponed, not immediate.
The one-and-only delay loop was like a fifth task added to the list above. Only once per iteration would there be a pause, during which the CPU would decrement the delay accumulator and repeat until it reached zero. This had the desired effect of enforcing a speed limit on all four tasks. I believe the technique is known as a "paced loop."
On my web site there's more info about the
discrete-TTL CPU -- including the actual schematic. Not much to it, but it ran those Diablo printers at 45 characters
per second. The noise was like a cross between a weed-eater and a machine gun!
-- Jeff
_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html
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