I'd like to optimize my circuit. It works right now, but I'm sure it can be better somehow.

What I'm doing now is using a 74hc374 latch. Since my address decoding is active low (and that low signal is needed elsewhere) I'm using an inverter on it so it'll clock the '374.

I thought instead, maybe I can use a binary counter's parallel load? (like the 74hc161) The parallel load enable is active-low. Only thing missing is the CLK. Would the CPU's Phi2 (aka M2) signal probably work for this use?

My main concern is that parallel load has to be enabled when Phi2 goes high. I looked in the 6502 datasheet's write timings, but I'm kinda confused (I didn't see Phi2 on it?).

OK, nevermind. I believe it'll work now.

But if anyone sees any potential problems with it still, let me know.

Memblers,

What kind of data are you latching? Address bus, data bus, IO data?

Will the data be relatched on every cycle?

Also, the 74hc161 only latches 4 bits. Is that enough or do you need 8 bits?

Daryl

I'm latching the lowest bits of the address bus. That's important to note, I'm glad you asked. I better take a second look at it. It's so I can do a 'STA $500E' for example and have $E latched (while a PIC's parallel port latches the data bus seperately).

If Phi2 causes it to be relatched several times, that's fine as long as it always latches valid address bits.

And 4 bits will be enough, I was actually only using 5 bits of the '374 and I won't miss the extra bit too much.

How fast is the PIC's response?

If you clock the counter(latch) on the rising edge of each 6502 clock PH2, can you ensure that the the PIC will not be trying to read the counter while the counter data is not stable?

Daryl

The PIC is running at 20Mhz now, I'm gonna try 40Mhz soon. But with at least 12 or so instruction cycles before possibly reading the latch, I think it's not too fast of a response.

The PIC is interrupted (at the highest priority) when the 6502 writes to it, and only reads the latched address/data at that time. So I'm pretty confident that it should always work, since the delay between 6502 latching and PIC reading would be very consistent.

And I also use NOP delays between the 6502's consecutive writes to the PIC, so it manages to stay in sync at the critical moment.

It sounds as if you've done all the what-ifs? Good luck with your project!

Daryl