Update: Pic

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I finished soldering in everything on top and bottom except the SyncRAM bypass caps.

Checked for short from power to GND and one did exist. After visually inspecting everything I decided to apply power to see where the smoke would come out, in order to save time. The top part of U3 (SyncRAM #2) let out a puff of smoke. After removing U3, the short was gone. After checking the PCB layout I did find where the Vdd & Vss were switched in 1 spot. I've absolutely no idea how that happened, but I'm happy that it's been resolved quickly. That would have been extremely difficult to track down.

I'm now attempting to get the old video project from PVB1 to pass synthesis with the new constraints and see if ISE recognizes the JTAG section.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Jeez, got 2 wires switched in JTAG! This board

ISE sees the FPGA and sees the SPI FLASH. It can program the FPGA very quickly direct, or it can program the 16Mbit SPI FLASH which is pretty slow. It verifies successfully using both methods, so this is good news at least. I can go on to experiment without having to pay for another set of boards.
I guess a reasonable goal would be to get the video working like it was on PVB1, although I'm done for a couple days I think. Time to start some seeds indoors for a summer crop.

Also, I don't think my SPI FLASH MUX circuit is going to work. I'll have to investigate multiboot from SPI FLASH. I've read of problems a couple years ago on the Xilinx forums. Maybe they have it sorted out now.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I couldn't keep away, I realized all I had left was to finish the .ucf constraint file for the oscillator input from the DS1085L...

Got the video working after abit of a struggle. First the board was being fed 5VDC, not the intended 3.3VDC. All the IC's seemed to tolerate this out of spec power supply voltage. At one point I'm sure the board was powered for over a minute. Obviously I don't recommend this.... Hmmm, now that I have it working, I will do another test with 5VDC and see what the video output looks like!

So after this voltage problem was corrected (long story), I got a very wavy and noisy picture. I figured it was either that I just semi-destroyed the IC's, or my bad bypassing scheme for the FPGA, or it was the source of the original clock which was the DS1085L. I was using the default output of 24.29MHz from the DS1085L and then used a PLL in the FPGA to achieve 149MHz for the project, 148.5 is necessary for 1080p standard which is what I'm aiming for. After wiring in a 100MHz can oscillator for the main FPGA clock, all noise and 'waviness' disappeared and I now see what I saw in PVB1. Success! I'm working on PVBV2i now and will order it soon.

Here are the Pro's and Con's of this current design as I see it:

Con's:
FPGA SPI MUX non-functional. Unable to fix.
JTAG wiring incorrect. Fixed and tested.
Power for SyncRAM2 incorrect. Unable to fix.
DS1085L unsuitable for video clock source.
VGA connector top GND improper spacing for VIA mount.
Power VIAs for main power connector need to be resized.
Still a PITA placing (0603,0805,1210) components.

Pro's:
The Xilinx FT256 1mm Ball Grid Array has been conquered with a Standard Operating Procedure.
Wiring between main IC's (U1/LX25, U2/SyncRAM, U4/videoDAC, U5/FPGA SPI FLASH) is correct and functional.
Bypassing scheme and internal power planes, for the FPGA and videoDAC, are functional and working well.
The manual use of solder paste and hot plate for QFP & SOIC IC's and discrete components (0603,0805) on top of the board was successful and much quicker.
The manual use of solder paste and hot air for SOIC IC's and discrete components (0603,0805,1210 & SOT-223) on bottom of the board was successful.
Main 3.3VDC Power In is 18AWG wire with 3 FT length. Will measure current...

Since the jitter on the DS1085L was unacceptable for video, and the 100MHz can oscillator I soldered in worked pretty well, I'm currently checking to see if a 200MHz oscillator would be even better for the FPGA to work with.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I forget to bring my DMM home from work! Tomorrow I must remember. I am expecting under 1.5 amp load for the 3.3VDC source.

The new design is almost complete for this board. It's going to be fun!
Instead of those DS1085L's, there is a USB to UART IC and a mini USB connector provision for a keyboard interface.
What is successfully done on one board will be replicated on the succeeding boards.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

200MHz external can oscillator source was noticeably better for the FPGA main clock and video output, when used by the internal FPGA PLL for 148.5MHz, compared to the 100MHz external can oscillator source. I don't know why this is yet.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

There's a 444mA draw on the 3.3V supply with the board running a static 1920x1080 display, with a few plotting errors. I believe it's a Verilog coding error in the line plot state machine. I've wrestled with it before.

The next version of the board, where both SyncRAMs are functional, should increase the load by another 300mA @3.3V per board, for the same static display. This is still under 1 Amp...

Way back, I've made a plotting program (for PVB1) that uses alot of blockRAM and the 65org16 to plot a dynamic display while manipulating a good chunk of internal FPGA BRAM. The current draw shouldn't be much more, but I'll test it tonight for S&G's.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Although this test isn't very scientific, thePVBV2h board only drew another 10mA for a dynamic display.
The current draw from the SyncRAM is already max'd, since it is always being read from for display data. The negligible extra current draw comes from the FPGA internals.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I was looking back at the K1 controller board design and noticed the erroneous VCC/VSS pin swap that destroyed 1 SynCRAM in this design was copied from that design. Both designs have been updated. Tomorrow the order goes in the EPCB queue for PVBV2.j.

Some critical parameter comparisons between the old PVB using a Spartan 6 LX9, and this PVBV2.h using a Spartan 6 LX25:
Number of Slice LUTs: 71% in original PVB. 27% in PVBV2.
Number of RAM16BWERS(FPGA 18-bit BlockRAMs): 96% in original PVB. 41% in PVBV2.

This is a seed of an idea for first testing:
The plan is to have 2 65Org16s, each controlling a Hardware Accelerated Plotter that plots to each of the SyncRAMs. The HAP will only output data when the SyncRAM is not selected to output data to the videoDAC.
As per BigEd's original idea, I plan to have a dual port FPGA blockRAM so the 65Org16's can communicate with each other, hopefully meaningfully. The software will determine this.
I still have to work out the internals. It's difficult to get back into the Verilog frame of mind, after the last 2 months of board design!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

PVBV2.j is in the 'chute'!...

I knew the first run (PVBV2.h) would be screwed up in some way, somehow, no matter how cautious I tried to be. So I had a very itchy 'trigger finger' to send the design off for manufacture more quickly than other designs I've done.
However, I'm confident the errors have been boiled out now, and in about a week it's time to start having fun again.

I'll explain more about the board's expected capabilities soon with the USB mini port and USER I/O connector.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

The mini USB connector (K7) on PVBV2.j should be able to connect to a modern PC through the FTDI230X as a slave device in order to receive data from a terminal program. I've done it before successfully at over 1Mbit/sec, although it was with an MCP2200. They also have Win drivers. I decided to try to expand my horizons since the FTDI IC has been highly regarded.

Also, the user I/O connectors (K4,K5), can easily be made to interface from the FPGA to an I/O Device with 8 signals, 2 clocks, power and ground. I plan to use it, initially, for a 6-pos mini din PS/2 Keyboard Interface. I will show how.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

No soldering yet. Just getting a feel for the placement.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Removed some SMD IC's from old boards using hot air station ( 898D+): 2 SyncRAM's, a 330MHz videoDAC, and 2 SPI FLASH FPGA PROMs. Also I rescued a Vreg diode for the videoDAC (very small part in upper left). This is a pic after ultrasonic cleaning. Soldering flux and finger oils are gone.
Tomorrow, I drink much coffee and get the board functional utilizing both RAMs!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Had to reinstall Win7 OS, something quirky with the 120GB SSD. I thought it was the SSD itself, but I plugged it into another SATA port and reinstalled the OS and things are looking better than last night when I was getting random BSOD.

I've made backups of everything pertinent since the very first signs of trouble, 2 days ago, even the custom PCB layouts for ExpressPCB.

You don't know how many times I've lost that custom PCB info and had to go back to an old layout to trim out and re-save the custom IC/connector layouts. This consideration adds speed to getting back 'up to speed'. I should have saved the ISE14.7 tarball.

Alas, I'm downloading it now and have 20 minutes left in order to truly test this board...

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Anyway, I did mount all IC's, cap's, resistors, LEDs and connectors. I would've hesitated mounting bypass cap's in the past because I was hand soldering those 0603 parts in by hand. With the solder paste and hot air, it's a breeze and very pleasing to see the parts line up when the solder paste reaches its melting point!

Also RE-mounted the 100-pin .5mm QFP SyncRAMs. Also a new 256-pin 1mm BGA LX25 Spartan 6 seems to have been successfully mounted. So far, it seems like a successful job.
I added more solder paste than necessary around both SyncRAMs, so some pins were initially bridged. As other members have pointed out prior, all that is needed is a wide tip soldering gun and some desoldering braid and the excess solder, creating the bridge between pins, is drawn out.

Before applying power, I measure initial resistance between 3.3V & GND @ 350ohms...

I applied power, and the LEDs light up:
There is 1 main white power LED.
Then there are 4 other LEDs, RGBY colors, connected to the FPGA for fun and/or testing. These turn on for about 1 second after main power is applied, then shut off. I think this has to do with the FPGA's HSWAPEN pin. In this project, the pin is grounded through a 4.7K resistor. IIRC this forces all pins of the FPGA high during powerup?, but before programming. So anyway, nice to see I got the polarity right for those LED's!
2 other LEDs present on this board are meant to show the status of the Tx and Rx lines on the FT230X USB to UART. Those do not light up yet, as I have that IC powered from the USB external


ISE14.7 is done downloading. I will test the first SyncRAM with the old project, and the 2nd SyncRAM with the old project to make sure all connections are solid.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502