Greetings everyone...

Has anyone figured out an "average cycles per instruction" for the 6502 or 65C02 instruction set?

I'm curious how the 6502 compares to a little CDP1802 computer I built recently. Since the '1802 uses two "machine cycles" or sixteen clock cycles per instruction (with only a few exceptions), it should perform about ~125,000 instructions per second with a 2-MHz clock. That seems slow to me and I'd like to compare it to a 6502 but I'm not sure how to come up with a similar calculation for a 6502 or a 65C02 running at 1-MHz. I realize "average cycles per instruction" is dynamic and dependent on code. Is there an accepted statistical range for average cycles per instruction for the 6502?

TIA... and I apologize if this is a dumb question...

Cheerful regards, Mike, K8LH

It's around 4 cycles per instruction, although it depends on what you're doing. A lot of indexing and indirects will increase the average. If you don't need those, and you can get away with a lot of ZP accesses, the average will be less than 4. So at 2MHz, that's 500,000 instructions per second. All 65c02's being made today are rated for at least 14MHz, which would be 3,500,000 IPS; but the off-the-shelf ones generally top out at about 25MHz if the supporting hardware is suited for it, which would be 6,250,000 IPS. The fastest ones are running over 200MHz, or about 50,000,000 IPS (50MIPS).

I've brought a lot of products to market with PIC16 microcontrollers, and when I was learning the PIC16, I took a lot of pieces of PIC16 code from Microchip's seminars and applications books and re-wrote them in 65c02 for learning, I found that the PIC16 generally took about twice and many instructions and twice as many clocks to do a given job.

Make sure you compare the interrupt performance too. From the time the 6502 receives an interrupt signal, through the average time it takes to finish the already-started instruction, run the interrupt sequence, and start on the first instruction of the ISR (interrupt-service routine), the 6502 takes about 10 cycles, or 10 microseconds at 1MHz. For extremely simple ISRs (like to just increment a byte in RAM each time an interrupt is received), it is not unrealistic for a 20MHz 6502 to handle a million interrupts per second.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thank you, Garth. A 4-cycle average is what I was using for a ball-park figure. It seems the little '1802 was a bit slower than some of its contemporaries of the time... Still, it's an interesting and cute little chip and it was CMOS which is kinda' cool...

Take care... Cheerful regards, Mike