One of the plus points on the gEDA pcb tool is it produces gerber files. Its then very easy to view them in an external viewer to confirm their content. I use the one at:

http://circuitpeople.com/

gEDA pcb does let you individually cover or reveal vias, and any other part, though I have never had to do this in my 2 layer, generally through-hole designs.

_________________
8 bit fun and games: https://www.aslak.net/

How did you create the vias EE? Is it a tool or button which allows either masked or unmasked vias??

Vias are created with a tool that unconditionally draws on both the upper & lower solder-mask layers. The mask layers are negative, so drawing removes the mask.

You can view the soldermask layers, one at a time. And you can draw extra stuff on them -- which is really an erasure, since they're negative. This provides you with a means to force a bare, unmasked area. But there's no complementary means by which to force an area which is masked.

And, ExpressPCB's solder-mask layers don't let you un-draw anything that was put there automatically. As with most CAD, you have to select a thing before altering or deleting it -- and, on the mask layers, ExpressPCB only lets you select stuff you drew yourself. The via dots were drawn automatically. They can't be selected, and I don't know of any way they can be deleted.

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Hmm, so in this particular tool, the only vias you can have are going to be free of solder mask? And yet in this case of the BGA, and presumably in most cases, it would be desirable to have the solder mask? Is this because of some aspect of the production process, or something about reliability in the field??

Edit: I see that vias in Eagle are non-masked by default, but can be tweaked, so you get "tented" vias. Some info at
https://www.sparkfun.com/tutorials/115

Despite the extremely close tolerances, I'm not ready to accept defeat yet Dr. Jeff...

Since $200 hangs in the balance if these boards are truly non-functional, I decided to throw another $28 dollars at it in the form of a 1mm 256-pin XC6LX9, lead free version I'd mentioned a few posts ago. I applied a thin layer of solder flux and very carefully placed the BGA within the 27mmx27mm square.

I was abit haphazard as I had the hotplate set to 230degC, when I put the board on it. After about 45 seconds, I remembered Pb free devices require higher temps for reflow. BTW I did not see the IC move 1 iota. Others here have mentioned that there IC's self centered or slumped when the solder melted which is another reason I thought the hotplate was not up to proper temp yet...

I found XAPP427, which might be useful to others attempting this sort of thing. It's best at least to aim close to spec.

It states on pg.4 for FTG256 packages a temp of 260degC is necessary. I'm going to try to reflow again at 260degC and then check for shorts.

EDIT: solder flux not solder paste

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

More power to ya, Sam! And certainly I never meant to imply you were defeated. Good luck, & keep us posted.

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Thanks for the FB Dr. Jeff!

I've ramped up the temp to 260degC and reflowed the board on the hotplate. It looks like the IC is a tad closer to the board

The initial test was for a VCCint power out from the ferrite bead after the U8 1.2V LDO VReg, and to see if any FPGA VCCint pins were possibly shorted to GND. Surprisingly, no short there as this is at the center of the FPGA. Chances are, either there are bad connections and no shorts, or I might get lucky.

A few more tests for shorts between powers and grounds.

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

I checked for more shorts between FPGA output pins and GND/Power planes and did not find any.
I decided the next best step would be to fire up the hotplate again and dismount the FPGA and see what it looks like underneath in order to try to see if all of the BGA pads 'took' the solder balls and to see if there was any intrusion by the solder balls into the via rings.

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

Gentlemen, I believe I have a victory here!!!

This USB 220x 5MP scope is indispensable!

My fears have been allayed.

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

Pre-hotplate pic with the smallest amount of solder paste for the QFP and SOIC packages. Still just flux for the LX25 Spartan 6, except this one is not Pb free. I dialed the hotplate back down to 235degC.

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

Post hotplate pic.... Time for a short check.

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

The solder didn't flow away from the pads - great news!

This is very good news!

I'm especially thankful it worked because my K1 Controller board was designed using this exact same process with a larger, more expensive 676-pin 1mm BGA. I'm less hesitant to order them now.
So the month or so spent on that design was not wasted, hopefully. Fingers crossed as I still have to make contact with the FPGA and SPI FLASH(s) using ISE14.7 and the dual SPI FLASH PROMs. Both boards have identical dual FPGA SPI FLASH PROM wiring.

I expect at least 1 FLASH to be seen by ISE... I must get back to soldering

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

For comparison's sake: The bottom board (PVB v1.0h) is fully operational, but it looks nasty with that old school (modified) IDE power connector and the 6-pin male SIP for JTAG is ugly.
PVBV2h is headed in a much better direction.

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

Update: All of the components on top of thePVBV2h board have been mounted, except for the Red, Green, Blue, Yellow, & White LEDs and current limiting resistors. These will be mounted later... The White LED is meant for a power on indicator, the other 4 RGBY LEDs, which are placed extremely close to each other, are meant for experimentation under control from FPGA output pins.

Before the night is done, the connectors on the top of the board will be soldered in. I might be able to post a pic.

Don't forget there are some wire wrap wires (blue) going to be present for some signals. The board was intentionally designed this way for some of the slower signals that program the FPGA upon startup.

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502