Rob Finch wrote:
...Just curious, could the address lines be shared on the RAMs or is it a bad idea ?
The RAM's data buses will be MUX'd by FPGA logic. Only 1 RAM will output data to the videoDAC (or next PVBV2) at a time. That way data can be modified freely on the other RAM by a cpu or hardware accelerator before the MUX is switched it's data is outputted. This switching will occur on VSYNC.
That's the idea anyway... Now, how to keep track of the progression of what is being displayed is something that I will have to investigate by trial and error which will be the fun part!
barrym95838 wrote:
It looks pretty nice EE, but the little engineer in my head tells me that your average trace length could likely benefit from rotating the FPGA and SRAM assemblage 90 degrees clockwise like so (rotating the actual chips 90 degrees as well):
Code:
OS OS OS
SRAM SRAM
U3 U2
OS FPGA OS
U9 U7 U1 U4
+======== I/O ========+
... where OS stands for "other stuff".
I know, I'm a stinker for even bringing it up at this stage of the game, but that little engineer in my head wouldn't leave me alone!
Mike
Yes it is late in the game! But thank you for your observation, it is very valid! One thing I can do that won't involve me starting from scratch is to move the Vreg at the bottom right of the FPGA further to the right, which would allow the videoDAC and a great many signals to be shortened.
I had focused on keeping the traces to the RAMs as close as possible, everything else was secondary. Those long traces you see are primarily for the RGB data in and RGB data out. PVBV2 design closely follows the original PVB design... And now that I think about it, those long traces
may have been contributing to some things that were happening but didn't realize at the time. i.e. some colors appeared to be 2 pixels wide IIRC. I was also using a slow videoDAC, ADV7125 rated @ 140MHz when the pixel clock was ~150MHz. I'm sure both were contributing... However thinking about it further now, if the Pixelclockout trace length was close to the RGBout trace lengths, maybe there would be no issue with the length? Irregardless, shortening the trace lengths of these critical signals cannot be a bad thing!
I'm also investigating a free PCB layout tool called
FreePCB, where one can just start laying down parts.