The RAM's data buses will be MUX'd by FPGA logic. Only 1 RAM will output data to the videoDAC (or next PVBV2) at a time. That way data can be modified freely on the other RAM by a cpu or hardware accelerator before the MUX is switched it's data is outputted. This switching will occur on VSYNC.
That's the idea anyway... Now, how to keep track of the progression of what is being displayed is something that I will have to investigate by trial and error which will be the fun part!


Yes it is late in the game! But thank you for your observation, it is very valid! One thing I can do that won't involve me starting from scratch is to move the Vreg at the bottom right of the FPGA further to the right, which would allow the videoDAC and a great many signals to be shortened.

I had focused on keeping the traces to the RAMs as close as possible, everything else was secondary. Those long traces you see are primarily for the RGB data in and RGB data out. PVBV2 design closely follows the original PVB design... And now that I think about it, those long traces may have been contributing to some things that were happening but didn't realize at the time. i.e. some colors appeared to be 2 pixels wide IIRC. I was also using a slow videoDAC, ADV7125 rated @ 140MHz when the pixel clock was ~150MHz. I'm sure both were contributing... However thinking about it further now, if the Pixelclockout trace length was close to the RGBout trace lengths, maybe there would be no issue with the length? Irregardless, shortening the trace lengths of these critical signals cannot be a bad thing!

I'm also investigating a free PCB layout tool called FreePCB, where one can just start laying down parts.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

After 7 hrs of some relocating, things are looking much better I think! But my head hurts. Time for a brew.
The videoDAC is much closer to the FPGA and the RGB I/O is more or less converging on the bottom right of the FPGA, instead of looping around the I/O connector.
Also, the relocation of the 1.2V VReg for the FPGA VCCint isn't really that much further, maybe 1/4".
Thanks Mike for your critique!
Notice, there's 5 free signals at the bottom of the FPGA circled in yellow, but unnamed. 2 are GCLKs. Also, 10 more signals were able to routed through at the upper right of the FPGA, 1 of those also a GCLK. These 10 signals might go to a .1" female user I/O expansion connector.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I couldn't stop development...
Mounting holes for K1 (96-pin I/O connector), K3 (VGA connector), K4 & K5 (User I/O) connectors have been placed. The K1 96-pin connector is now perfectly centered and the board resized. The final board dimensions are 3.682"x2.5". All unassigned pads routed from the FPGA are now labelled. Some good potential is there...

There's just a few things left now:
1) Finish output stage of videoDAC.
2) Finish U5 & U6 SPI FLASH FPGA PROMs.
3) Document the system.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

More comments on this anomaly:

I remember experimenting with different resolutions and slower pixel clocks and system speeds and the anomaly was still there. For instance, if a purple line was drawn and one were to put their face 2 inches from the monitor one could see a red line and a blue line side by side. At 1920x1080 resolution it is very difficult to capture with a camera, unless the camera settings are perfect for this sort of thing, so I never posted it although I did try to capture it. Anyway, I believe it was not a hardware issue as I would see this anomaly come and go as I modified the Verilog hardware accelerator under many resolutions and pixel clocks. If the anomaly was hardware related it would have shown up and disappeared under predictable circumstances, especially speed related...

In order to try to improve the performance of PVBV2 some ideas that will be implemented:
1) The 330MHz version of the ADV7125 videoDAC will be used on the final PVBV2 output board.
2) Ground the VGA connector shielding. On the original PVB, it was not grounded, only pins 5 and 10 were grounded.
3) Use inductors on the RGB output stage from the ADV7125 to the VGA connector. I had followed the ADV7125 Datasheet for PVB, a 'typical connection' snapshot from it is below which shows the ADV7125 in action with no inductors present. Below that is a snapshot from Analog Devices CN0282 which shows the inductors, and that CN worked up to 1600x1200 @165MHz.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

It is almost complete!

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Since I'm not following Xilinx' rules on their recommendations for proper power supply bypassing, I'm debating on adding power supply filtering for the 3.3VCCO/AUX for the FPGA and also the 3.3V analog for the videoDAC in the form of an inductor and 2 cap's for each supply, sort of like Analog Devices does in their Connection Note (CN0282). Can anyone give me some tips on the values to shoot for? It looks like their values aim to filter out switching noise from their switching power supply IC's (ADP2301).

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

L1 & L7 are necessary parts of the switching regulators, and the layout of those is very critical to get good behavior, that being especially important for the analog portions of your circuit. Are you laying out that part of the power supply though?

F1 through F7 are ferrite beads. Check out this one: http://www.mouser.com/ProductDetail/Lai ... YbBQ%3d%3d (or others in that family). How much current do they need to handle? Make sure you have ones rated for it so they don't saturate and lose their "choke" value.

Next, get the 0.1uF chip capacitors as close as possible to the power connections they go to on the chip, to get the lowest possible inductance for an AC path from that power pin or ball to the ground plane. For BGA, that will probably mean putting it on the back of the board, on the side opposite the IC (although I have not done any BGA layout to speak with any authority about how to do that). You can get those in 0402--maybe smaller (since you can get by with a WVDC of 16V or even 10V)--but I don't know if you're able to mount something that small by hand. Small is good for reducing inductance though. Take a look at this article from Dr. Howard Johnson on minimizing bypass capacitor inductance. The capacitors that are 33uF in your diagram don't have to be as close.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Ah, I missed the fact that they were ferrite beads! I assumed they were typical inductors based on the inductor sign but missed the F1-F7 part numbering. Thanks for pointing that out!

I can't get a bypass cap next to each of the BGA power pads, which is why I was thinking the next best thing would be to isolate the BGA 3.3V with it's own power plane and filtering, same for the 3.3V analog section of the videoDAC.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Every board needs a mark...

I was bored today, so I made some imaginary gears into my design. Happy Birthday somebody, heh.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Looks like something into which a designer could really sink his teeth.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Indeed! Board design appeals to the OCD within me, but being a disorder it starts to take a toll... My apologies. Not that I have OCD. Not diagnosed anyway..

Some progress:
1) I've started the .ucf constraints file which assigns FPGA pins for ISE to program the FPGA.
2) Also, by moving a few pads under the FPGA, current will flow much better for the 3.3V. You can see there's more space around the vias now, none are trapped. Compare to previous pic above.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I believe the PVBV2a has been finalized.
All the design goals have been reached for this board layout and now I feel like $200 is a price I'm willing to pay to get this thing rolling!

I've added 2 more power planes that are filtered using a ferrite bead and a few capacitors, within the 3.3V main power plane shown at the bottom pic.
One plane is for all the FPGA VCCO/VAUX pads, I count 25. The layout provides for a 0805 ferrite bead, a 0805 cap, and 2 0603 cap's. 6 amp rating of a ferrite bead this size are more than enough, as well as 33uF for an 0803 cap. I decided on a ferrite bead with a rating of 22ohm @100MHz, based on the Analog schematic I had posted above.
The other plane is for the analog 3.3V power of the ADV7125 videoDAC. The ferrite beads and caps are all 0603 sizes as the current demand is much less.

Any critiques welcome! Thank you.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

It appears that all parts are on the top. Is that correct? If so, I think it would be good to put the power layer on the back, so it's not between the signal layers and the ground plane. The power layer has big chainsaw cuts in it, making it unsuitable as a plane layer for any signal traces that cross the cuts. I think your ground plane is continuous though, right?

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Correct, but I can't change layer assignments. I think it's SIG-POW-GND-SIG. I'm just going to have to go forward and hope for the best.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Garth, I interpreted your 'jagged' comment to mean diagonal so I tried to come up with a better layout:

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65Org16:https://github.com/ElEctric-EyE/verilog-6502