Folks,

Terminal confusion here... I'm going bananas looking at timing diagrams for stuff I *knew* twenty years ago

Please reassure me: the 6502 wants the data bus only when phase 2 is high/phase 1 is low, yes?

I *really* ought to know this...

Cheers,

Neil

That's basically right. There is a read hold time where when the processor is reading a byte from the bus, the data must be kept valid for a few nanoseconds after phase 2 falls, but that usually happens automatically anyway from propagation delays and the bus capacitance holding the data. Similarly, the processor will keep data on the bus a few nanoseconds (at least 30 for older, slower processors, 4MHz & down) after a write cycle so the devices it's writing to have a chance to latch it in. Bus capacitance may hold it even longer into phase 1, which doesn't hurt anything.

Thanks Garth - I can get on with the design now

Neil