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hoglet
PostPosted: Thu Dec 11, 2014 8:10 am 
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Hi all,

A quick question to help a friend Roland over on Stardot get his new Acorn Atom design working.

What are the occasions where a SY6502 will issue exactly two successive write cycles on the bus, as observed here:
http://www.stardot.org.uk/forums/downlo ... &mode=view

The only one I can think of is a JSR instruction pushing the program counter onto the stack, but wouldn't that have a dead cycle in between (where SP is decremented)?

IRQ and NMI would be also include the status registers.

It's possible this is a hardware bug, as the design is still being debugged.

Dave
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BigEd
PostPosted: Thu Dec 11, 2014 8:21 am 
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JSR was my first guess too, but in fact any RMW instruction (increment, decrement, shift, rotate) will write back the old value and then write back the modified value. See the INC instruction starting in cycle 12 at
http://www.visual6502.org/JSSim/expert. ... f&steps=40
and
http://en.wikipedia.org/wiki/MOS_Techno ... and_quirks

This applies to all the NMOS variations - the CMOS chips perform extra reads instead of extra writes.

Cheers
Ed
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hoglet
PostPosted: Thu Dec 11, 2014 8:29 am 
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Yes, I just spotted that one in the bug list:

http://en.wikipedia.org/wiki/MOS_Techno ... and_quirks

Quote:
The 6502's read-modify-write instructions perform one read and two write cycles. First the unmodified data that was read is written back, and then the modified data is written. This characteristic may cause issues by twice accessing hardware that acts on a write. This anomaly continued through the entire NMOS line, but was fixed in the CMOS derivatives, in which the processor will do two reads and one write cycle. Good programming practice will generally avoid this problem by not executing read/modify/write instructions on hardware registers.


Thanks,

Dave
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GARTHWILSON
PostPosted: Thu Dec 11, 2014 9:22 am 
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Quote:
The only one I can think of is a JSR instruction pushing the program counter onto the stack, but wouldn't that have a dead cycle in between (where SP is decremented)?

No, the writes are in successive cycles, with no dead cycle in between.  In the interrupts, there are three writes in a row, two for return address and one for status.  This is covered in the 6502 interrupts primer.  This diagram is in it:
Attachment:
figure_1.gif
figure_1.gif [ 20.1 KiB | Viewed 198 times ]

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BigEd
PostPosted: Thu Dec 11, 2014 10:29 am 
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GARTHWILSON wrote:
Quote:
The only one I can think of is a JSR instruction pushing the program counter onto the stack, but wouldn't that have a dead cycle in between (where SP is decremented)?

No, the writes are in successive cycles, with no dead cycle in between.

Indeed, the incrementing of the stack pointer is done in parallel.
Previously:
"Q. When is the stack pointer not the stack pointer?"
A. During JSR, the SP goes off to the ALU to be incremented and the S register is used a temporary register to hold the high byte of the destination.
(Link to a visual6502 simulation)
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8BIT
PostPosted: Thu Dec 11, 2014 7:49 pm 
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Don't forget the BRK instruction as it also has three successive writes.

Daryl

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