Quote:
http://www.6502.org/documents/datasheets/wdc/wdc_w65c22s_mar_2004.pdf
is really not complete for the description of the 6522! I think it is rather a starting point for experiments/tests!
Actually the data sheets are pretty complete-- not 100%, but close to it. Sometimes it seems like something's not there until you struggle over a problem for a long time, and when you finally get it figured out, you go back to the data sheet, and find the information was hiding there all along but there was no big red font calling your attention to the part that's easy to slip on. I've included a few things that aren't there, like that the proper sequence to get T1 running in free-run mode is to set up the ACR and then write directly to the counters, followed by writing to the latches later if you want to. That's something I got from an ap. note a Rockwell engineer faxed me years ago. The data sheets also won't tell you about the one bug with shifting under control of an external shift clock, but that's irrelevant when CB1 is
outputting the shift clock.
I mostly use my Synertek data book for the VIA just because that's where I have all my notes, highlightings, etc.. Of course I keep in mind a few improvements in WDC's VIA, like that it has symmetrical totem-pole outputs and its inputs are high-impedance instead of presenting an LSTTL load. What the data sheets won't tell you is all the things you can do with the VIA. They just give you the sterile facts and it's up to the user to be creative in what can be done with the tools provided.
Quote:
thesylph005 asks if port B should be set to output mode in order to generate a continous square wave on the CB2 pin!
GARTHWILSON answers to this:
At reset, PA and PB are set to all inputs, not outputs. To make a bit an output, write a 1 to its corresponding bit in the data direction register. Making PB all outputs would require storing FF to VIADDRB.
Well this is true but not the answer to the question!
thesylph005 did not specifically link the PB output question with the CB1 & CB2 lines, so my assumption was that he wanted to use PB for something else in the project. I understand though that my answer could be confusing. The CA and CB pins are controlled by the ACR and PCR, not DDRA and DDRB. In my own many uses, I have always treated the ports' bit data direction as unrelated to the CA and CB pins. When they're used for the handshaking spoken of in the data sheet, it's mostly for things like feeding data to a parallel printer; but I've never used them that way even when I
was feeding data to a printer with the VIA. There's more than one way to skin a cat. Anyway, the CB1 and CB2 data directions for shift register usage are set by the ACR bits that determine the shift register operation mode. One of our products flying in aircraft all over the world without problems uses the VIA's shift register without ever touching the PCR at all, anywhere in the program.
Although I have not specifically re-quoted all the earlier questions, this should provide answers. When questions seem to make wrong assumptions, it's sometimes more productive to change the approach.
Regarding CB1&2 data directions: When you're using the shift register (SR), the first of the three binary digits determining the SR mode tells the CB2 (data) direction. 0=input, 1=output, like bits in DDRA and DDRB. The next bit tells if T2 is used. 0=yes, 1=no. The last bit of the SR mode control is not quite as simple, but it will never be 0 when using an external shift clock source. I never really thought about it this way. I just look up the mode I want in the table in the data sheet.
Quote:
If somebody (Garth?) knows exactly how the shift operations work why not describe it!
I've used this IC a lot for scores of things. There's probably more that I'm forgetting to tell, but I'll be glad to keep answering questions as long as they come up. Sometimes the review is good for me anyway, and sometimes someone will ask something that drives me to try out something I'm not sure of.
In response to Mats' last two paragraphs: T2, when used separately from the shift register, is one-shot only. But when you use it with the SR, it does keep re-loading itself to start each new bit. Unless you're using SR mode 100, it will stop after the 8 bits are shifted in or out. If shifting
out, the data on CB2 will retain the last bit's value until you give the SR another byte to shift out. T2 restarts itself for each byte. It is not necessary to keep writing to T2.
If you set up a SR mode that uses T2 even when T2 was already being used for something else first, it gets re-assigned to the SR. I have not tried this one, but the data sheet seems to be pretty clear on it, showing that T2 will count phase-2 cycles and not PB6 pulses for example. T2's high counter byte is ignored in SR use. (That information is hiding in the data sheet too.)
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