The SPI serial flash memories I've used were a bit complex in that there are lots of different commands, but none of them are hard to understand. I just followed the diagrams as I wrote my programs, and things worked right on first try. If one is serial, bits will go in and out one at a time anyway, so it's up to you whether you want to group the the bytes into words or long words or whatever; but the basic chunk of data will be a byte, then so many bytes in a sector, block, etc.. The serial interfaces sure make construction easier since there are so few lines to connect.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

This is great info then Garth.
I had thought the internal SPI FLASH memory had different data lengths that would be shifted out depending on the spec's DigiKey stated for various IC's but now I think understand...
I'm more of a parallel person myself but I'm willing to invest in an experiment with high speed (75MHz) serial SPI, especially since the onboard array of SPI FLASH will be 1Gbx16.

EDIT: Finished wiring the SPI FLASH's and SD card, it's abit gnarly. Also, there's a jumper for the last /CS from the 74154 to select either the last FLASH or the microSD card. Last to wire in are the RF transceivers. Ah, I almost forgot I need to have a true hardware random number generator discussed in this thread.

EDIT: 11.23.2014 Corrected SPI FLASH size

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Gnarly it is, the SPI FLASH Array wiring. Added a pulldown resistor on the SCLK per PG.16 of the Micron datasheet. Still need to add pullup resistors on all the /CS lines coming out of the 74154. Gonna get more gnarly...

Also been doing some research into white noise generator circuits based on Zener diodes. Maxim seems to be the company that can supply the amplifiers. They even have an App Note regarding this from 2005, which I had posted a link to in the appropriate RNG topic earlier today. It uses a MAX2650 that needs a 4.5-5.5VDC supply. Unacceptable in my case.
I'll have to investigate improved IC's they have to offer since then, one's that can operate in the same frequency range but lower operating voltage... I hope to have a voltage doubler or quadrupler circuit based on a diode-based charge pump circuit I saw on Garth primer site. The Zener diode only needs 10mA, but the voltage has to be rather high. The Maxim AN uses 14v for the Zener supply.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

What zener is it? It seems to be pretty standard to run a zener diode at 10% of its rated power dissipation, which I suppose is because that's where you start getting into the steepest part of the curve without wasting excessive power; so a 1/2W 14V zener would be run at 500mW/14V/10=3.6mA.

The voltage multiplier circuits EE is referring to on my site start at http://wilsonminesco.com/6502primer/potpourri.html#PS . Near the bottom of the section are recommendations and links to several 8-pin ICs I've used for voltage inversion and doubling. The circuits for those are at the links. They're quite easy to use.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

It's a 1N571. EDIT: 1N759, sorry.
I'll upload the PDF, thanks for analyzing Garth.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

After a little research into white noise generation, I came across the MM5837 IC mentioned in the RNG thread in the hardware section. I checked out the datasheet and saw it was a PRNG (pseudo random number generator), just like the one I am using currently, except it has a random seed value upon power-up, which is really all I desire.
In the RNG thread, Arlet had mentioned doing just this by reading random values from the RAM just after startup. I would feel comfortable with this idea if I was using conventional static RAM, as I've seen patterns are totally random.

I will do some tests next 2 days on 1 PVB which uses a 2Mx18 Synchronous RAM. Maybe a valid test would be to read the first 16 16-bit values of the 1920x1080 display during power-up and plot/ record the values. After a recorded time powered down, measure IC temp, then replot values.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Also, the project has reached a certain number of holes again
Damn they get you with the holes, while offering real estate. For EPCB 4-layer ProtoPro max holes is 650. The project currently has 726.
So now I have to go with their Production 4-layer service which will cost $318US for 2 boards. For comparison, 4 boards would cost $350US.

This project has the potential to be a $500 ball of wax that will melt in my hands and be a total waste if nothing works.

I don't like this, I will try to eliminate 76 holes for 4 boards @ $195

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Bah, I'm confident in this design and I will not waste time again conserving vias. I remember now that this was what took so much time for the final version of the PVB's. I imposed the strict via limit on myself only because I needed 6 PVB's and I could get 3x 3.8" x 2.5" boards for $98 using their Miniboard service. 350 holes is the limitation.

I will have to accept the fact that I will be using EPCB's 4-layer Production Service for this controller board. It is sort of a motherboard after all.

Not bragging here by any means, but I must begin to put everything into perspective in this final stage of the K1 Controller design. I must look @ Cost vs. functionality: Cost is No Object in my design because it is my hobby, but the functionality must be maximized for the $$$ spent.

Wiring for the 2 RF modules is almost complete, this is the last stage of wiring & parts placement. After this, checking, checking and rechecking + some trace optimizations. I expect 2 weeks for this.

Done:
Finalized the RF section.
Moved the HDMI audio section closer to the HDMI video connector and away from the RF section.
Added 2 more reset switches for each of the 2 900MHz RF transceivers.
Added 2 right angle thru-hole connectors for the antenna's mounted @ 45 degrees. An articulating base allows the antenna to swivel 90 degrees and rotate 360 degrees. Screw RP.

Things to do:
Finish wiring RF transceievers.
Finish the parts list (BOM).
A block diagram of the board.
A block diagram of the total system.
Schematics for small certain portions of the board.
Expected capabilities.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I see a number of unused pins on the 96 pin I/O connector. Can you switch to a smaller connector and thus reduce the hole count?

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I was actually trying to find another 96-pin connector with < 1mm spacing. No luck. To answer your question though, it would be a waste at this point.
So far I have 5 PVB's. The bottom pic is the mainboard with the 96-pin backplane receptacles soldered in and 2 expansion connectors not soldered yet. Switching the 96-pin connector is not trivial task... I actually started the design around this connector as it fits nice on a 3.5" x 2.8" board.
The bottom pic shows (from the left):
An expansion board, not used.
K1
PVB1
...
...
...
...
PVB6
Expansion board. Output signals from PVB6.

The new PVBs will have 2 SyncRAMs each. Doubtful I'll be able to use the $98 service, but this is far in the future.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Burning the midnight oil. It is just about complete.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Hi EEye, you can get 96-way connectors with only 64 positions loaded. Perhaps other possibilities too. I don't know how that will fit with your pin assignments.

Impressive-looking system with all those boards in parallel though - a scalable collection of FPGAs with local memory should be able to do all sorts of things.

It's worth some experience points, though: you find yourself with a limit on holes, so your general approach of maximising functionality until the board is full needs a refinement: don't keep adding things until the board is full, but also keep an eye on hole count and stop when you've used up your hole budget.

Similarly, if you have a limited hole budget it means you need to take care when choosing connectors and architecting your interconnect. Serial connections and shared busses will use a lot fewer holes than point to point busses.

Engineering is all about budgets and tradeoffs!

Cheers
Ed

You have a point there BigEd. I was aiming for filling in the 21sqin afforded by the 4-layer ProtoPro service. I had actually forgotten that I had a limitation of 650 holes with that service. When I used the portion of the PCB program that checks for errors and lets one proceed to order boards, I discovered I was over the limit.
Well now that this design is 99% complete, the hole count is at 798. Even if I got rid of the HDMI Audio section and the 1Gx16 SPI FLASH Array, I'd still have ~80 more holes to eliminate.


Each of the SyncRAMs have their own separate address and data busses because I'm trying to implement a strategy that does away with the snow effect by using 2 frame buffers for the video. I also have an idea for 2 65Org16's to read/write to the SyncRAMs depending on which SyncRAM is outputting data (to the videoDAC/actually the 1st PVB), while sharing data in zero page by the use of dual port zero page blockRAM. With the XC6SLX45, I may actually be able to implement the full 64Kx16 zero page dual port BRAM. Credit to you BigEd for the original idea!


I'm very sure there's other possibilities, I can't think of any yet. Too busy, but feel free to express your ideas!

Always, but I try to never sacrifice performance!

I burnt on the board layout, gonna start with block diagram next.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

First, I apologize for quoting myself so often...
I'm still proceeding with ExpressPCB's 4-layer Production service.
This is going to be slight feature creep, but I've been looking at the SSM2604 Audio Codec IC. Since I'm in the 4-layer Production service now, the 21sqin board limitation is gone. The new limitations are 12"x14".
Keep in mind, I'm a fan of hi-performance audio. It seems today's hi performance audio is through a 24-bit ADC/DAC, although it is serial. This SSM2604 has 2 24-bit ADC's and 2 24-bit DAC's.
I'm blabbering. 1 final addition I would like to add is an expansion connector for digital audio out to another dedicated audio board. There appear to be enough pins on the northeast of the FPGA BGA that are presently unused. I would just have to expand the vertical length of the board in order to incorporate this connector.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Added some test points in the form of .050" BGA pads for critical clock signals, and just a couple of test pads for serial data.
Some other optimizations are in there as well.

Origin is at the upper left. In order to expand the board, first I'll have to change the bottom RH coordinate in order to expand the vertical length of the board. Then, I'll copy the entire design and paste it to the bottom RH. I don't need more than 1/2". When I do this, the connectors/switches on the top will have to be re-spaced in order to line up with the audio expansion connector which will be present on the upper RH.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502