Any idea on the resistances involved? And the resistances of vias? I noticed quite a few layer changes in this layout, but it might not amount to anything significant.

Remember I'm a beginner. Also I'm using some somewhat painful software. That board is entirely hand routed.

Yeah the vias on the power rails weren't ideal. I haven't noticed a measureable resistance across a run with the most vias. But like I said they are not ideal. Luckily they are well made.

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Other things come into play here. One is the thickness of the copper. On outer layers, 1oz copper is pretty common, but you might have 2oz. If you didn't specify, see what the board manufacturer does as standard. 1oz copper is 0.0014" thick. As far as what the trace itself can carry, an 8-mil (0.008") trace of 1oz copper can handle half an amp at a modest 20°C rise. That's probably a lot more than most would expect. The other thing is how much voltage is would drop, and that of course depends also on the trace length. The resistivity of copper is about 0.67µΩ-inch, meaning a 1" cube of copper has 0.67µΩ of resistance between the ends. So to get the resistance of the trace, multiply that by the number of inches of length of the trace (let's say 3" for the sake of discussion), and divide by the cross-sectional area of the trace which in the case of your 0.040" trace of (I'm assuming) 1.4"-thick copper is 0.0014"x0.040"=0.000056 sq. in.. 0.67µΩx3/0.000056=36mΩ. Yep, 36 milliohms, nowhere near the 1.3 ohms of the fuse. If you had a quarter of an amp running through that 3" 0.040" trace then, it would drop 0.25"x.0.036=0.009V, or nine millivolts.

All that is to say don't worry about your trace width. It's totally fine.


That's actually good. Autorouters do a poor job, and I'm not aware of any that can place or move parts during autorouting to get good density.


The length of vias is too short to worry about them much for resistance. If you like, you can fill them in with solder to reduce the resistance.

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What's an additional VIA among friends, anyhow?

Sheet resistance is usefully expressed in Ohms per square. It's relatively easy to estimate the number of squares in a short track by eye, or of course you can divide the length by the width. That track you describe - 1.4" long and 40 thou wide - is 35 squares, and so your calculation that it has 36mΩ resistance tells us that tracks of this thickness have 1mΩ per square. That's easy to remember!

[Edit to add: elswhere, I see "Spoiler summary: The sheet resistance of 1oz copper foil is about 0.5mΩ per square."]

(Less helpfully, I can tell you that a wire with an eighth of an inch diameter has a resistance of one Ohm per kilofoot. See http://wiki.xtronics.com/index.php/Wire-Gauge_Ampacity which might be an interesting site to browse.)

Cheers
Ed

Speaking of ground/supply issues, good PCB layout can keep inductance to a minimum -- even using ordinary, skinny traces.

Of course the ideal ground "rail" is a plane extending across the entire area. But a grid of ordinary traces can come close to the same effect (with a comparatively fine grid naturally yielding better results than a sparse one). This diagram from an old RCA app note illustrates the idea. Of course it doesn't matter which traces are on the top or the bottom as long as you get a pattern of more-or-less horizontal & vertical paths -- with a via at every junction.
Aslak3, I hope you don't mind if I show a spot where your design could benefit from closer adherence to this approach.Your grid has a gap -- a missed opportunity. It would've been good to run a ground trace from cpu pin 1 toward the right, joining with the other ground trace near pin 40.

Of course there are dozens of signal traces, and for each of those circuits the return current is carried by the ground/supply traces. One of the circuits that's particularly affected by the missing link is the circuit that connects the CPU with C1 & C2 (associated with the crystal). Although the left ends of C1/C2 have nice, direct connections to the CPU, the return path for those capacitors' current is substantially longer than necessary (as shown in yellow). If, as suggested, there were a ground trace from cpu pin 1 toward the right, the return current for C1/C2 wouldn't energize such a big loop. And keeping the loop area small is how you minimize inductance. (In case anyone's wondering, wider traces are of little use in reducing inductance because they don't reduce the loop area.)

-- Jeff

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