Hi,

I'm thinking about a IO Bus and for this I wanted to slow down the CPU only for IO access, but still keep it in sync with a IO PHI2 signal, and came up with the following schematic.

it is some sort of state machine. PHI2IO is the PHI2 signal for IO peripherals. Together with PHI2Q it builds up a 2-bit Johnson counter. This uses FF1 and FF2. FF3 is used to generate the PHI2 for the CPU. /SLOW is the output of the address decoder which should be asserted whenever an slow IO request in Sync with PHI2IO occurs. Typically it will just be /LOW if the CPU emits a address in the IO Page. PHI2IO will go to PHI2 of the 65xx peripherals. PHI2C goes to PHI2 of the W65C816 and PHI2CB goes to LE of the 74AC573. If required /Q1 will provide the complement of PHI2IO. So when not accessing IO the CPU runs a half the oscillator speed and when doing IO it will be synced to PHI2IO which runs a one quarter of the oscillator which is half the CPU speed

I tried to draw the states in Excel (see the PDF).

Everything is still on paper, but I wanted to ask if someone can have a look into it and tell me if there is an obvious error before I put it in real hardware on my breadboard.

Cheers

Peter

Why not just use RDY and wait-state bus accesses?

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

cbscpe,

I've had a think about your design and I believe it won't work the way you have drawn it. I think that you have the wrong inputs to the 74HC151 and they should be as follows

0 = Vcc
1 = SLOW'
2 = SLOW'
3 = SLOW'
4 = Gnd
5 = Inverted SLOW'
6 = Gnd
7 = Gnd

Tying input 3 low and input 5 high on the 74HC151 results in clock stretching on cycles that don't access I/O - I think the whole point was to avoid this. With these pins corrected, state 6 comes into play and this input needs to be tied low instead of high or you will again be stretching cycles that don't access I/O.

BDD's suggestion about using wait states will work if you are using a cmos 65C02. (It won't work with an NMOS 6502 which is why the BBC Micro had a cycle-stretching circuit. I must confess, your design is far more elegant than the one Acorn used by the way. ) However, the logic needed to generate the RDY' signal will be similar to what you already have, so there is no real advantage either way.

(Edit - removed inconsistencies in text)

_________________
Shift to the left,
Shift to the right,
Mask in, Mask Out,
BYTE! BYTE! BYTE!

I was thinking the same thing -- the RDY approach would certainly work. But it might not be any easier. The problem is not entirely simple, assuming we want the timers in a VIA, say, to run undisturbed. If they're to maintain a steady, free-running, half-time tick, that means the CPU is obliged to sync up to where-ever the peripheral clock happens to be in its cycle. IOW it isn't always a single wait-state that the CPU requires.

Hmmm, I'd say it's almost a Johnson Counter! To my eye, it appears to lack a signal inversion in its loop! Peter, I don't have time right now to fully digest what you've done, but I redrew your diagram in a way that I find clearer. Does this seem accurate? But there's a booboo in the original, and I think a correction needs to be applied (as shown).

cheers
Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

I tried the same with using RDY, but ended always with a solution much more complex using additional gates and open collector devices. I also studied Andres Wait State generator, but was not happy with it. I wanted something "simpler" (where "simpler" means as seen by myself, which obviously must not be the same for everybody). At least my idea is very "small", because it just replaces the normally used 74AC74 (to generate PHI2 and /PHI2 for the Bank Address Latch) with a 74AC175 and adds one single IC a 74AC151.


I'd say the same of course, you need to feed back the inverted output of the last stage. My Error, thanks for spotting this.




Not quiet sure I understand your point. In normal operation, that is no access to IO, i.e. /SLOW is not asserted (means it is high) the machine will continuously run through states

1->7->2->4->1

states 3 and 5 will not occur.

/SLOW must only be checked before PHI2C goes high. So it must be checked in states 1 and 2; inhibiting PHI2C going to high if /SLOW is asserted. This either results in the machine to go to state 0, if it was 2 or go to state 3 when it was in state 1. In the first case we are already in Sync with PHI2IO and can proceed to state 5, which is the start of a long PHI2C=High phase so PHI2C will be high again and this results in state 7. then 7 goes to 2. In the second case (we are now in state 3) we are not in sync with PHI2IO, there is no other way than to stay low and so we proceed to case 2. Now /SLOW is still asserted (PHI2 of the CPU did not change so all outputs of the CPU did not change as well and as /SLOW depends only on the state of Address lines /SLOW has not changed either and is still low), so we will proceed to 0 which is the same as the first case.


Cheers Peter

Ahhhhh. When working out the state machine inputs, I only considered the current state and what should follow it. I didn't consider that some states could only be entered under certain conditions and so need only progress to a particular next state. It would appear that the problem has more than one solution. And that you thought about it more deeply than I did.

And I have to admit to embarrassment that I missed the fact that your Johnson counter needed an inverter!

_________________
Shift to the left,
Shift to the right,
Mask in, Mask Out,
BYTE! BYTE! BYTE!