Has anyone got one of these wired up and programed on a C64 or C128?
I can enable chip and write(WRN), but the read enable(RDN) is not simple thing to get working.
I am trying to connect directly to buss. I don't want to go thru an interface chip to talk to this interface chip.
thank you

What exactly is the issue with the RDN signal? As far as I know the select signals (IO1, IO2, ROML ROMH) on the expansion slot of the C64 are not qualified with PHI2 and can directly connect to /CS of the UART. Using a 74HCT138 to generate WRN and RDN should work just fine. The same as you would need to do with any 6502 based system (and what I do in fact and what works flawless on my tiny 6502 system). Bus load should not be an issue if you only connect a SCC2691 on the expansion slot.

May I direct your attention to this post?

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Ok its a timing problem. The Gal16 in the sample may have just enough delay to make it work.
I was thinking they were fast? The 2691 calls for RDN to go low with CEN low if I do both at the same time it doesn't work.
The Gal seems to be obsolete now. I asked for a quote from some obsolete parts places for going back to R6551.
The one quote back from 4STAR $20. With all this work for obsolete parts I think I will just go
with something new I can program as a UART. The Parallax Prop chip at $8 will give me lots of options. I have done projects
with the Prop before. I was thinking it was overkill, but keeps things interesting.

My datasheet says that A0, A1, A2 and CEN must be stable tas=10 nanoseconds before RDN or WRN is asserted. So taking both CEN and RDN down at the same time will definitively not work. Its much the same as with 65xx peripherals, register select, read/write and chip select signals must be stable a minimum time before the leading edge of PHi2.

I'm in the process of adding one to my existing 65C02 setup. The SCC2691 has an inverted Reset line compared to the 6502, so it has to be inverted to work. I'm using a 74HC00 to interface to the 65C02 bus. Three of the gates are used to generate RDN and WRN signals (qualified by Ph2 clock) and the remaining gate inverts the reset signal. How are you handling these signals on the C64?

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Regards, KM
https://github.com/floobydust