Best I can find is £19.61 for 16Kx8
http://uk.farnell.com/integrated-device-technology/idt7006l15jg/sram-dual-port-16k-x-8-smd-plcc68/dp/1260371

_________________
Andrew Jacobs
6502 & PIC Stuff - http://www.obelisk.me.uk/
Cross-Platform 6502/65C02/65816 Macro Assembler - http://www.obelisk.me.uk/dev65/
Open Source Projects - https://github.com/andrew-jacobs

Oops, it looks like I made the classic mistake and found a 16kbit dual-port SRAM instead of a 16kbyte one. Sorry about that.

An 8k x8 CY7C144E-55AXC can be had for £11.23 or an IDT 7005S35PFG for £15.95

And a 16k x8 CY7C006A-20AXC costs £18.14 or £18.34

(I'm not even sure if 20% VAT might need to be added to those prices, sorry.)

Ed

That's about $30 for us in the US You would probably have to look at using another chip for isolation if you wanted to sell it to the community.

Just a quick note to mention that propagation delay needn't prevent adoption of this approach. FET-based bus switch ICs are available which can, for a project like this, replace the '244 tristate buffers which superficially seem to be required. FET bus switches boast near-zero propagation delay. IOW a ROM emulator could use such ICs to connect or disconnect the target system with an ordinary RAM chip, and that chip needn't be any/much faster than the ROM being emulated.

Attached is info for one such IC -- but the overall selection is startlingly extensive. Some of the FET bus switches also offer level-shifting -- useful when connecting devices operating at different supply voltages.

--Jeff

ETA: The FET switches aren't quite a perfect solution, however, as they occupy space on the board and in the budget. And there'd be an increase -- probably tolerable -- in capacitive loading on the target sysytem. So, the dual-port ram still bears consideration.

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Given that the fastest E(E)PROM I've seen has an access time of 55ns, and you can get SRAMS with an access time of 10ns or less, is the propagation delay for the buffer even an issue?

Also, as an alternative to isolating the ROM emulator from the target CPU, it may make sense to have a flying lead to isolate the target CPU instead (obviously places some requirements on the target system).

Thanks for posting, and you're right -- we do have RAMs that are fast enough to allow for the delay of tristate buffers. (The delay is double, since there'll be one buffer to receive the address and another to send back the data.) But the FET bus switch may save money by allowing use of a comparatively slow RAM. The FET bus switch itself costs around $0.50, about the same as the '244 or similar device it replaces.

I wanted to bring attention to the FET bus switches anyway, simply because of the intriguing possibilities they offer -- such as the level-shift aspect. Also these devices are inherently bidirectional -- and that applies even to the FET versions of unidirectional devices such as the '257 (quad 2-to-1 multiplexer). IOW a FET '257 can also be used as a demultiplexer. http://www.ti.com/lit/ds/symlink/sn74cbtlv3257.pdf

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Two ideas for using a fast ARM-based chip to emulate a ROM without need of a dual port RAM:

- The new model Raspberry PI has about 26 general purpose I/Os but they are not 5V tolerant.

- The STM32 F4 Discovery board has even more, and is 5V tolerant.

A slightly out-there idea, but... how about emulating an EEPROM or FlashROM such as the SST39SF0x0 series or {AT4,Am2}9{F,LV}0x0 series, including the ability to erase and re-program the emulator in-situ and then be able to download the reprogrammed data back to the host PC? Yes, these are 1-4 megabit (128k to 512k byte) parts, but that's a fairly typical size range for 8-bit and 16-bit video games (for example), and I know that it's in the range for things like modem firmware.

I often use W29C020C, but the fastest I could get were 90ns, they were made with 70ns but that's the end of the row. They are flexible indeed, have a software protection protocol and you can define bootstrap regions you can't erase easily or accidentally. On the other hand I also use dual-port RAMs for my VGA-Video Adapters (IDT7134 with 4kbyte) and I'm thinking about to use them as the boot-strap memory. They are not very expensive (10USD/piece plus 7USD shipping for 55ns versions). I also thought about to use a AVR MCU that can take complete control over the 6502 bus (using BE) and preload the 'ROM' range of the (now always fast) RAM. This does not give you the USB interface, but only a serial interface to down/up load images but at least you have all in-place options. I prefer serial interfaces so I don't have to deal with USB-Drivers on the host system. Transfer protocols (XMODEM and ASCII) are very small and easy to implement and are built into most terminal programs. A ATMega328 with two 74HCT595 (for A0 to A15) should do the job. This gives you 32kbyte of flash, you will need some for the AVR program, but it will definitively leave enough for the 6502 ROM Image.

See also the new Teensy offerings, much faster and with more I/Os, and one of the two models is 5V tolerant. It has USB. And it's in DIL format (but with too many pins!)
https://www.kickstarter.com/projects/pa ... -35-and-36
viewtopic.php?p=46835#p46835

I made mine using an SRAM, Buffers and an OR gate

While programming the buffers isolate the SRAM and hold the system in RESET

JP2 & JP3 plug into my raspberry pi, JP1 connects to a ribbon cable with one of these on the other end.

It would be pretty simple to attach to an AVR instead.