Thanks Daryl and Rich, this is making more sense now. Rich has confirmed he's using the same firmware with the exception of an additional font. Since the font shouldn't alter timing, let's assume it is not the issue. In looking at Rich's VOutput routine and the one in Daryl's ZIP they're in same ballpark now, with one small difference.
Here's Rich's SBC 2.7 OS:
Code:
VOutput
bit Via2PRB ; read handshake byte (pb7)
bmi VOutput ; if pb7=1, wait for AVR to be ready
sta Via2SR ; send to display via shift register
VOutput1
bit Via2PRB ; read handshake byte
bpl VOutput1 ; if pb7=0, wait for AVR to ack
rts
This is in Daryl's firmware ZIP archive:
Code:
VOutput
bit vportb ; 4 read handshake byte
bmi Voutput ; 2/3 if 0, wait for AVR to be ready
sta vsr ; send to display via serial port
VOutput1
bit vportb ; 4 read handshake byte
bpl Voutput1 ; 2/3 if 0, wait for AVR to be ready
fast LDY #$80
LDA #$00
VLOOP DEC
BNE VLOOP
DEY
BNE VLOOP
rts
They're identical except for what looks like a substantial delay loop before the rts in Daryl's code. That loop could significantly slow the 6502's frequency of VOutput calls, but the SBC 2.7 OS is doing a whole bunch more than Daryl's sample. For now I'll assume the two VOutput routines are effectively identical.
Which makes me think the ATMEGA88 firmware is getting wedged and never altering the pin state. I was looking at the schematic and it claims that the ATMEGA88 is reset when the 6502 is, but I've noticed that often the only way to get the system unstuck is to power it off and power it back up again. I don't know if that is significant or not.