The 28nm Xilinx 7 series have some major improvements of the 45nm 6 series and for it to be cheaper I have to go for it! A short story first...

Recently I've had some success with a 144-pin QFP Spartan 6 (XC6SLX9-3TQGC) in a high speed video project. Looking back at the BOM, this device was $17.22. Looking today the price is the same. Amazing.

Anyway, there have been discussions here in the Programmable Logic section about mounting 1mm BGA. A member enso says he has had great success with mounting these devices using a custom made hotplate. I think he went on to favor the 484-pin Spartan 3A. Soon I jumped in and made a custom hotplate as well. To this day I have not tried mounting any 1mm BGA, but the hotplate functions well. enso commented somewhere that it is easier to mount 1mm 256-pin BGA than .5mm 144-pin QFP. It was around this time (about a year ago) that I began to seriously think about slightly enlarging the video board project to incorporate a larger Spartan 6, the XC6SLX25. It's currently available for ~$45.

After a breakthrough working with some very fast 4ns Synchronous RAM running at 148.5MHz I began to think even more seriously about redesigning the board and searched out the best Xilinx FPGA that could fit a 1mm 256-pin footprint. I came up with the Artix 7 XC7A35T-1FTG256C. Although it is the slowest version, it is only ~$38 and it is in stock. The highest speed version (-3) is ~$55 with a 6 week factor lead time, which is no problem since the board is not even designed yet. But before designing the board, I would like to attempt to migrate the design first.

So looking at ISE14.7 and doing a quick search on Xilinx forums, I realized that ISE only supports the larger Artix devices. I will have to download Xilinx' new Vivado free webpack to design with the smaller XC7A35T. I'm doing that now, and will try some experiments to see how the project fits. Currently the 4-board project has only the output board operating and running at a pixel clock of 148.5MHz. The 65Org16.c together with a hardware pixel accelerator are running at 74.25MHz. The Spartan 6 is getting close to being maximized, Slice LUTs and Occupied Slices are what I have my eye on after making changes to the Verilog. Here is the current report. With simple coordinates from the cpu, the accelerator can:
Draw Line
Copy/Paste
Pixel Plot
Fill (simple rectangular)
8x8 Character Plot (background/foreground colors)
Pixel Color Read

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

Interesting to see that there's a new design tool - for the 7 series, and only the 7 series.

Here's the PDF which allows you to compare Spartan 6 with Artix 7:
http://www.xilinx.com/content/dam/xilin ... -guide.pdf

For full details, see
http://www.xilinx.com/support/documenta ... /ds160.pdf
http://www.xilinx.com/support/documenta ... erview.pdf

Most Spartan 6 boards seem to choose the XC6SLX9 aka LX9. The smallest Artix 7 has 3x the amount of on-chip block RAM and about 3x the logic capacity too. The Spartan 6 docs speak of memory controller blocks, but the Artix 7 ones don't - perhaps the point is that the 7 series is big and fast enough not to need dedicated blocks. Anyhow, the 7 series can drive memory faster - not that we tend to visit the high performance memory arena.
http://www.xilinx.com/products/technolo ... terfacing/

The FPGAs themselves may be reasonable cost, but I didn't find any cheap dev boards - perhaps it's too early. Trenz have something for EUR 300 or so.

Cheers
Ed

UG586 has more information on memory interfacing here. I've not looked at it yet, but I've downloaded all the data sheets and user guides.
Trying Vivado now...

In case the link breaks in the future they are:
UG475 7 Series FPGAs Packaging and Pinout Product Specifications User Guide ( ver 1.11, 24507 KB )
UG470 7 Series FPGAs Configuration User Guide ( ver 1.7, 4258 KB )
UG471 7 Series FPGAs SelectIO Resources User Guide ( ver 1.4, 5596 KB )
UG472 7 Series FPGAs Clocking Resources User Guide ( ver 1.10, 3111 KB )
UG473 7 Series FPGAs Memory Resources User Guide ( ver 1.10.1, 2056 KB )
UG474 7 Series FPGAs Configurable Logic Block User Guide ( ver 1.5, 2544 KB )
UG483 7 Series FPGAs PCB Design and Pin Planning Guide ( ver 1.9, 2936 KB )
UG479 7 Series FPGAs DSP48E1 Slice User Guide ( ver 1.7, 1427 KB )
UG480 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide ( ver 1.4, 3057 KB )
UG482 7 Series FPGAs GTP Transceivers User Guide ( ver 1.7, 9001 KB )
UG586 Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions v2.1 User Guide ( ver 2.1, 18838 KB )
UG769 LogiCORE IP 7 Series FPGAs Transceivers Wizard v2.6 User Guide ( ver 4.6, 7158 KB )
UG429 7 Series FPGAs Migration Methodology Guide ( ver 1.0, 578 KB )

Also:
DS180 7 Series Overview
DS181 Artix 7 Data Sheet

UG768 Xilinx 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide for HDL Designs ( ver 14.7, 7302 KB )

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

I added UG768. It is the HDL "bible" for the 7 series.

I have some reading to do.
Vivado doesn't like the Verilog 'wor' statement.
In fact it seems to be favoring VHDL outputs for the IP cores.
I have a sine LUT using a Spartan 6 IP core. It uses the RAMB16BWER primitive. This is not present on the 7 series.
'wor' was easy to fix.
Working with this IP generaor in Vivado is going to require experimentation..

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

I've not given Vivado a significant try out. The few attempts to use it resulted in the quick removal of the monstrosity from my PC. To be fair, I had the same reaction to all versions of ISE before ISE 8.2i SP2. So I will look for post from you regarding your experience with the tool.

_________________
Michael A.

Yes it's a large install. ~5GB download and 10GB disk space needed.
2 problems Vivado didn't like. One is the 'wor' statement in Verilog. I adapted the code with an assignment X = A| B| C | D. The other problem was migrating the LUT table made by ISE's coregen tool. I tried to use the update command in Vivado but it didn't work correctly. Vivado has it's own coregen equivalent. Trying it to make the LUT table from scratch with some difficulty assigning correct pin names. It generates VHDL files and they are not editable as far as I can tell. Will have to experiment some more tonight.

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

In addition to:
UG768 Xilinx 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide for HDL Designs ( ver 14.7, 7302 KB )
there is also:
UG953 Vivado 7 Series libraries

It gets confusing when one is forced to use Vivado for some smaller 7 series parts. I assume UG953 is for this purpose?
Whereas one could use either ISE or Vivado for the larger 7 Series parts.

I'll ask my stupid question on their forum.

EDIT: Maybe I won't. this post asked ISE or Vivado:

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502

This Vivado is a whole 'nother beast to learn. I'll tackle it off and on. However, I'm not going to be posting on learning Vivado.
One note as it was running synthesis. I saw a notice ISE has never given me before in regards to the 65Org16.b/c core microcode state machine. I had an overlap in there for column A opcodes. So while a PLX, PLY, PHX, PHY should have had a state of PULL0 or PUSH0 respectively, they also would've had a state of REG. I never noticed an issue in performance but it did shrink the SLICE LUT's and OCCUPIED SLICEs by 1%. Updated Github.

_________________
65Org16:https://github.com/ElEctric-EyE/verilog-6502