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PostPosted: Tue Jan 04, 2011 8:47 pm 
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I discovered an interesting logic family not too long ago, called Integrated Injection Logic, or I2L. Signetics seems to have been a large-scale user of this technology. It boasts 1V supply rails using complimentary bipolar transistor circuits. For example, here's a typical inverter, expressed in the best ASCII art I can muster on work hours:

Code:
            +Vcc
            ---
             |
             |
             \
              v|
           Q1  |---o +Vbb
              /|
             /        -----> Y=!A
            |        /
            |      |/
  A o-------*------|  Q2
                   |\
                     v
                     |
                    ---
                    ///


+Vbb is usually derived on-chip, and is typically 0.65V less than +Vcc, where +Vcc typically = 1.0V to 1.25V. The inverter works because Q1, a PNP transistor, is configured as a constant current source for Q2. If A is high-impedance (e.g., if A is high), then Q2 will be turned on by the current supplied by Q1. This brings Y low. Conversely, if A is low (tied to ground), then the voltage on Q2's base falls below 0.65V (typically 0.25V based on my measurements with 2N3904/2N3906 transistor pairs), thus turning it off, leaving Y in a high(-impedance) state.

Now, I know that I2L is ancient technology, but for its day it was earth-shaking, because it was very low power. A single NOR gate (the basic I2L gate) implemented with discrete transistors (let alone on-chip transistors!) could draw as little as 5 microwatts of power, if my math is right. So, in theory, a 6502 implemented in I2L could reasonably be expected to draw as little as 20mW of power, give or take some reasonable amount of tolerance for uncertainty. Let's call it 50mW to be conservative. Because it was current-mode, the logic was pretty fast too, being a bit faster than TTL of the day.

Could this logic make sense for use on a backplane bus, and if so, how would it be terminated? I ask because the PNP transistors seems, to me at least, to function in the same capacity as an active bus termination circuit. This would suggest plug-in cards would drive the bus with open-collector logic, and the backplane itself would implement the PNP current sources, to be shared by all the logic. This arrangement seems like it'd fundamentally alter how one should terminate the bus, if it's required at all.

What are your thoughts?


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PostPosted: Wed Jan 05, 2011 10:14 am 
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(only tangentially related: in the late 70's and early 80's Ferranti in the UK made gate arrays with capacities around 700 usable gates, which were used in Sinclair and Acorn machines. The arrays used Current Mode Logic, which has a load resistor so isn't quite the same thing. Chris Smith's excellent book says the gate consumption, at a 0.95V array supply, was 3uA for a 450ns gate delay in the low power versions, up to 210uA for an 8ns gate delay in the high speed versions. The chips were TTL compatible at the pins.)


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PostPosted: Mon Jun 23, 2014 7:27 am 
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kc5tja wrote:
Could this logic make sense for use on a backplane bus, and if so, how would it be terminated? I ask because the PNP transistors seems, to me at least, to function in the same capacity as an active bus termination circuit. This would suggest plug-in cards would drive the bus with open-collector logic, and the backplane itself would implement the PNP current sources, to be shared by all the logic. This arrangement seems like it'd fundamentally alter how one should terminate the bus, if it's required at all.

What are your thoughts?

To prevent reflections, a transmission line needs a matched, constant-impedance load. A constant-current source will not have a constant impedance (nor will an open-collector output.) I suspect it would reflect falling edges more than rising edges; but I don't know how to calculate it. I'm not sure a LaPlace transform fits the bill. If I had to write a program to simulate it, I might brute-force it by chopping the transmission line up into a gob of L's and C's which respond to time, and have a load equation (or an array representing the voltage-versus-current graph) which is only DC, ie, does not depend on time, and set up a loop to do tons of iterations. Hmmm...

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PostPosted: Sun Jun 29, 2014 10:13 am 
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Hello,
for what i know the best way to absorbe reflection in bus terminatio is the array of shottky diodes (no dissipation, high speed)

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PostPosted: Sun Jun 29, 2014 7:10 pm 
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granati wrote:
Hello,
for what I know the best way to absorb reflections in bus terminations is the array of Schottky diodes (no dissipation, high speed)

At https://web.archive.org/web/20080705140 ... s/2_19.htm, Dr. Howard Johnson says the problem with the diodes is
  • they are far from perfect, so they absorb only part of the initial overshoot and do nothing about the ringing (and the possible double-clocking) that continues from not absorbing all of it, and
  • they are not fast enough for the job in high-speed digital.

Keep in mind that CMOS ICs already have Schottky diodes for static protection from every input to Vcc and ground, yet there's still a big problem. If there truly were a perfect diode, it would become a short to Vcc when the voltage exceeded Vcc by even a tiny bit, or to ground if the voltage went below ground by even a tiny bit, and shorts do reflect power back to the source, just in opposite phase from what open circuits do.

This one is also interesting: Severe Overshoot Mailbag

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PostPosted: Mon Jun 30, 2014 1:43 am 
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GARTHWILSON wrote:
granati wrote:
Hello,
for what I know the best way to absorb reflections in bus terminations is the array of shottky diodes (no dissipation, high speed)

At http://www.sigcon.com/Pubs/news/2_19.htm, Dr. Howard Johnson says the problem with the diodes is
  • they are far from perfect, so they absorb only part of the initial overshoot and do nothing about the ringing (and the possible double-clocking) that continues from not absorbing all of it, and
  • they are not fast enough for the job in high-speed digital.

Keep in mind that CMOS ICs already have Shottky diodes for static protection from every input to Vcc and ground, yet there's still a big problem. If there truly were a perfect diode, it would become a short to Vcc when the voltage exceeded Vcc by even a tiny bit, or to ground if the voltage went below ground by even a tiny bit, and shorts do reflect power back to the source, just in opposite phase from what open circuits do.

This one is also interesting: http://www.sigcon.com/Pubs/news/3_1.htm

I'm feeling deja vu all over again, as we had this discussion elsewhere. The article you reference is from 1998 and represents Dr. Johnson's thinking based upon the available Schottky diodes of the time. Schottky clamping arrays have gotten very fast compared to what was available 16 years ago. Individual diodes have reverse recovery times in the 4ns range, and clamping arrays, as one might use on an address or data bus, are typically in the 8ns range.

The static protection diodes in CMOS parts don't clamp at the five volt level, so I would have to question their effectiveness in suppressing bus reflections. That said, I don't see where reflections are going to be a problem in a system running at the speeds we usually use, unless the lines are significant in length.

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PostPosted: Mon Jun 30, 2014 2:09 am 
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Quote:
Individual diodes have reverse recovery times in the 4ns range, and clamping arrays, as one might use on an address or data bus, are typically in the 8ns range.

The overshoot time on an improperly terminated line driven by 74AC or ABT can still be too fast for those diodes to respond.

Quote:
I'm feeling deja vu all over again, as we had this discussion elsewhere. [...] I don't see where reflections are going to be a problem in a system running at the speeds we usually use, unless the lines are significant in length.

The post at viewtopic.php?f=4&t=1728&p=33837#p33837 addresses it.

Quote:
The static-protection diodes in CMOS parts don't clamp at the five-volt level, so I would have to question their effectiveness in suppressing bus reflections.

Hmmm... I just checked some memories and some 74HC, AC, and ABT logic ICs with the DMM on the diode test setting, and they show 0.45V-0.65V drop on those diodes, meaning they're probably standard silicon, not Shottky like I thought and which would be under 0.25V. I put the negative probe on the Vdd pin and the positive on logic input pins, then the positive probe on the ground pin and the negative on logic input pins.

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PostPosted: Wed Jul 02, 2014 9:48 am 
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Hello everyone,

http://www.ti.com/lit/ds/sdfs093/sdfs093.pdf

this explain how work shottky diode barrier.


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PostPosted: Wed Jul 02, 2014 6:18 pm 
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granati wrote:
Hello everyone,

http://www.ti.com/lit/ds/sdfs093/sdfs093.pdf

this explain how work shottky diode barrier.

It raises a good point, about the capacitors in series with the resistors. The diodes only clamp voltages below ground, but the real termination is the 50-ohm resistors in series with the 47pF capacitors. The capacitors let the resistors do their terminating job without putting a DC load on the driver.

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