It's no secret that 5V logic is disappearing, and that in the near future, getting recent 5V glue logic (GALs, CPLDs) will not be possible. As someone who prefers to use new chips that are "fresh out of the fab (i.e. still manufactured)", this concerns me for a few reasons:

1. I may have difficulty getting replacement parts or upgrades in the future.
2. I can no longer use modern tools to program them. Although considering I use a 286 to program EPROMs, that might be a bit hypocritical .
3. Newer parts have speed and power consumption improvements due to advances in IC fabrication... using new-old stock, I lose these benefits.
4. I'm not sure how to interface a 3.3V part to a 5V circuit with a minimum of parts! See this Xilinx forum post. All of the suggested solutions involve converting the FPGA I/O side to open-collector inputs and use pullups, which I can done before for a 430 with 3.6V logic. But that was just the pullups and that was for 4 inputs. CPLDs would need one diode+pullup for each PIN that I use! The other issue is that, while 3.3V CPLDs will output a valid TTL signal at 3.3V, Garth has mentioned to me before that the '816, when operating at 5Volts, doesn't strictly accept TTL inputs, and 3.3V input is too low.

Unlike some other members here, I'm not very interested in the 6502 as it was used in old computer systems. I'd rather use 5V-tolerant parts which are still manufactured to this day, and use recently-fabricated parts (including the 65c02, and '816, whatever changes they may have gone through since their inception in the early 80's). I was wondering if anyone has had any experience successfully interfacing a modern FPGA or CPLD to other modern 65xx family chips and 5V logic, and how they were able to do it without requiring 84+diodes and resistors?

Yes, I can run my '816 at a lower voltage and sacrifice clock speed, but there's enough 5V interfacing to older parts (outside of my 65xx computer) that I'd like to do to justify using a 5V supply. Call it "an uncomfortable mix of old vs new" .

The FPGA modules from OHO (called GODIL and GOP) include level converters to provide 5V compatibility - might be worth looking into. They are very wide, but not cheap. They are bidirectional - there's an enable input but no direction input.
74CB3T16211, 24-way, about £3, http://www.ti.com/lit/ds/symlink/sn74cb3t16211.pdf
The 16-bit wide 74ALVC164245 might be useful, and is about half the price - it's directional so you need a control to say which direction you're driving in.

Edit to add: Michael, below, has successfully used TI's 4-bit level shifter TXB0104PWR which costs about £1 and has a 7.4nsd propagation delay.
http://uk.mouser.com/ProductDetail/Texa ... 9GpMWq5w==

Also, I'd missed out the convenience, where possible, of using 3V3 parts which are 5V tolerant, as noted below by Marco.

BDD notes below that Atmel seem solid with their support of 5V operation, so that's another way to go.

Yeah, "an uncomfortable mix of old vs new" indeed.

I've successfully combined 3.3V with 5V on MARC-2. The DUART, RAM and AVR are powered at 5V and the VIA's CPU and CPLD at 3.3V. while the CPLD has 5V tolerant I/O.

The IC's are from right to left:

ATMega1284P at 5V
512kB 55ns SRAM at 5V
XC95288XL TQ144 CPLD 3.3V with 5V tolerant I/O
WDC65C816S at 3.3V running stable at 7,3728MHz
2 x WDC65C22S at 3.3V

The lower left corner:
MAX232 at 5V
74HCT74 at 5V
SC26C92 at 5V

The lower left corner:
RV-3049-C2 at 5V (Real Time Clock with temperature sensor)

If the '816 accepted the 3.3V coming from the CPLD as a logical "1" while running at 5V, I'd be very happy, but unfortunately it doesn't. I'm still glad it runs at 7.3MHz though. I made several errors during the design, and even after building it I had to reroute the DUART's data lines to the right 5V RAM side of the CPLD.

It surely is about making compromises. But with this design I still have the opportunity to connect 5V devices to the expansion connector (around the CPLD).

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Marco

Nice looking computer! I'll keep your idea in mind, but 3.3V '816 is out of the question since that lowers the maximum speed. I'm going to at least TRY to run my first simple computer at 10Mhz (it will probably be redone from scratch after I get an initial working design).

cr1901:

I posted regarding a project which has an example of the type of the circuit you are asking about. You can follow the link to the project's GitHUB repo for the part numbers. They can be found on sheet 5 of the schematics.

The project uses some new TI level shifters for interfacing a 3.3V FPGA/CPLD to a 5V external device. In the example circuit, the TI level shifters interface a 3.3V FPGA to a 5.0V Arduino UNO. In the picture at the link, the devices are on the right side, just above the Xilinx JTAG connector. (On a commercial product, I have also used these devices to interface a Spartan 6 to a 80152 5V microcomputer. The devices allowed the FPGA to replace all external 5V parts needed to implement a typical ROM-less 8051-compatible system.)

The drive capabilities of the devices are limited. In my applications, only one or two 5V CMOS loads are expected, so high TTL drive is not necessary. I expect that if you require a lot of drive you can use one of the dual-rail '245-style level shifters available from a number of sources. I opted for these devices because they allow bidirectional signal flow, and therefore allow pin-by-pin I/O matched by the programmable nature of the FPGA I/O pins.

I no longer attach these SMT devices to my boards without visual aids, and their pin pitch generally will require solder mask in order to avoid solder bridges. For the project to which I have directed you, I simply paid for some professional assistance in its physical assembly. Since I spend most of my time working the FPGA/CPLD logic, the time saved by this approach provides some measure of sanity in the face of declining physical capabilities.

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Michael A.

Atmel continues to produce 5 volt CPLDs in quantity. Their AT15xx series is a standard part that can be programmed via JTAG or with Atmel's programming rig. You can use WinCUPL to write, compile and simulate your code if you have a Windows box. There are other ways to program their PLDs if you don't have Windows at your disposal or don't want to use it.

It appears that Atmel is trying to fill the 5 volt void created by other companies exiting that market. From their website:

Atmel CPLDs: Industry Compatible
The ATF15xxAS/ASL/ASV/ASVL CPLD family offers pin-compatible supersets of the popular Altera 7000 and 3000 series devices ranging from 32 to 128 macrocells with propagation delays from 7.5 to 15 ns for 5V standard power versions and 15 ns for 3.3V versions. Atmel's proprietary low-power ("L") versions use Input Transition Detection (ITD) to power down the device automatically when nothing is switching. All devices also support JTAG in-system programming (ISP).

The Logic Doubling™ features of the ATF15xx family make these products ideal for new designs. The ATF15xx family offers the most powerful switch matrix and routing resources of any CPLD while also supporting multiple independent feedbacks, individual output enable, global clear and D/T/latch configurable flip-flops. More global clock pins, a programmable pin-keeper and the ability to realize two latches per macrocell are further examples of the enhanced features available from this CPLD product family.

There is nothing on their website to indicate that this product line is going away any time soon. My POC V2 unit will use an ATF1504AS in a PLCC44 package for glue logic. POC V3 will use the ATF1508AS (PLCC84).

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Thanks Michael - I've added a note to my comment about the TI 4-bit level shifter TXB0104PWR

I also don't like running my '816 and two VIA's at 3.3V.

What I don’t understand is why Vih of the '816 is 4V when supplied with 5V. I find that rather annoying, otherwise I could drive the '816's data bus directly with the 3.3V CPLD. Or am I interpreting the data sheet incorrectly?

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Marco

Yeah, it is a bit disappointing. Also a potential pitfall for the unwary! Some IC's like the Rockwell 'C02 accept TTL levels on their inputs (because measures have been taken to lower the input threshold voltage). As you suggest, that means a 3.3V signal is acceptable as a logic high. But WDC's '816 and 'C02 have inputs whose switching points are roughly symmetrical with respect to 50% of the supply voltage. IOW, no TTL compatibility, and 3.3V is not reliable as a logic high.

Luckily, level shifter IC's are available in high-density versions. For example, the 74LVX4245 is an 8-bit bi-directional device ideal for use as a bus transceiver. And the 74CB3T3384 is a 10-bit device that can be used to take 5V signals from the '816 (such as the address lines) down to 3.3V.

Those devices are just two examples. I haven't done the research -- there's a bewildering assortment of such products available (including some .1"-footprint devices). But naturally it would be nicer to reduce the package count by rolling it all into a CPLD. (Thx for the Atmel tip, BDD.)

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Million-dollar question: How much propagation delay do these level shifters add? I wonder if it's possible to run the 6502 reliably at 20 MHz within a circuit containing level shifters...

I randomly picked one from Jeff's list, the 74CB3T3384, and read the specs. Prop time is about 7.5ns operating on 3.3 volts. That would be tolerable with a 65C02 (not 6502) running at 20 MHz, as long as you aren't piling on the glue logic. Other factors get into the picture, of course, and you'd have to beware of signal skew issues as well.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I was looking at a number of these level shifters some time back, and IIRC it was typically between ~6ns and 11-12ns, depending on the chip. I believe there's a difference between bi-directional and unidirectional types for example. And there are several variants of bidirectional too. TI and Jameco and others have datasheets.

-Tor

I expect it has to do with the fact that the WDC parts can run down to 1.2V, unlike 74HCTxx which is 5V only.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

This is interesting because these WDC parts can still operate at such a low voltage, which equates to a lower speed for their IC's, but I think it makes them voltage compatible with the higher speed (RAM) devices in this present age.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Well, it does make them supply-voltage compatible, but as you have to drop the supply voltage you will lose clock speed - unless you have suitable level conversion in place.

(That's my take on the discussion anyway)

Cheers
Ed