(First, some context. Then some notes about the reset logic in the NMOS 6502)
In a thread elsewhere about 6502 behaviour, MichaelM
exhibited a datasheet showing the differences between the NMOS part and a particular CMOS part, the California Micro Devices G65SC02:
MichaelM wrote:
Jac:
Garth pointed me to this
datasheet. In Table V there's a good discussion of the behavioral differences between the NMOS and CMOS 6502s.
That prompted me to make an observation about the reset behaviour:
jac_goudsmit wrote:
BigEd wrote:
Interesting that this device pushes three bytes to the stack at reset. On the one hand, it allows a reset to work as an interrupt (it knows what what happening and can even return) but on the other hand it's making a change. Previously I've opined that it's better not to write. But on reflection, when the stack is always in page one, it's unlikely that anything of interest would be overwritten.
(Going off-topic, that's okay)
The WDC 65C02 also appears to handle a reset as a half-ass interrupt: during three of the six reset cycles, it appears to read from three decrementing(!) addresses in the stack area.
I suspect that handling all three signals (~IRQ, ~NMI and ~RESET) the same way (pushing the flags and PC onto the stack) made sense in the electronics design, but the team at MOS decided to add an extra gate or diode or PLA entry to change the three stack pushes during reset from writes into reads so that no memory would be affected by the reset. And apparently the company that made this 6502 clone decided to leave that gate out.
Indeed, nothing of interest is likely to be overwritten unless you're in a very restricted system (e.g. a system with just a 6532 or 6530 where the zero page and stack are likely mirrored). And one could argue that when the system is reset, it shouldn't assume anything about the state of the RAM, so who cares if it writes something to the stack. But I reckon Chuck and Bill and the guys figured that one extra gate to prevent writes wouldn't change the size of the chip too much, and would save a lot of headaches in cases that they couldn't possibly foresee.
I wonder how hard it would be to find where the stack pushes during reset are changed into reads in Visual6502.org.
===Jac
jbevren wrote:
The 6502 has apparently always handled /RESET as an interrupt with the exception of stack writes not following through. This and some other very low level items were covered by Michael Steil in 27c3. You can see his presentation on youtube (search: [27C3] (en) Reverse Engineering the MOS 6502 CPU, make sure you include (en)). If anyone's remotely interested in how interrupts are processed, or especially why a NMOS 6502 jams up when it executes a $02 (or most $x2) opcodes, watch Stiel's presentation.
Regarding design choices on working with /RESET, that would make some sense as it could save on logic cost.
That YouTube video is probably
this one.
I had a look using visual6502 and also the
giant schematic (pdf) by Balazs Beregnyei.
It turns out that there's an extra transistor to suppress the writes during reset. The crucial signal is called C1x5 in the schematic, and C1x5Reset in the visual6502. It's produced near lower right of the schematic, or
here on the chip:
Attachment:
File comment: This corner of the 6502 - bottom right in Balazs' schematic - derives the internal signals Reset0 and C1x5
reset-and-C1x5.png [ 25.75 KiB | Viewed 1958 times ]
Here's the C1x5 signal in action, the logic is a bit lower left of dead centre of the schematic:
Attachment:
File comment: The RnW logic takes in the C1x5 signal
C1x5disablesRnW.png [ 25.56 KiB | Viewed 1958 times ]
Here's a 6502 simulation showing the latching of the reset value, which is held until the end of the BRK sequence, and which suppresses the three writes to the stack.
Attachment:
6502-reset-no-writes.png [ 106.39 KiB | Viewed 1955 times ]
Here's the crucial pull-down transistor t3455 on the chip.
Cheers
Ed
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