I know it's a horrid abuse of programmable logic, but I'm wondering if it's possible to create an astable multivibrator in Verilog?

Why?

To complete the 6525 effort, I need to create a 500uS delay period. It doesn't have to be precise, just >= 500uS. I otherwise have no need for a clock signal. Thus, I was wondering if it would be possible to put the 10uS CPLD into a feedback loop, count 64 transitions, and use that as a timer.

Jim

I'm no Verilog expert, but seem to think that a simple(?) state machine may accomplish what you want. However, I'm not sure how you would go about achieving an ~500µS delay without use of a clock input.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

Keep in mind that the 10ns (not µs) is a guaranteed maximum, and that there's no guarateed minimum. I suspect typical would be somewhere around half to 2/3 of max.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

If you have a spare input and output, a resistor and capacitor will give you some approximation to any delay you want.

and even if there are no Schmitt-trigger inputs, you can approximate one by adding positive feedback with resistors, to avoid problems with the "no-man's land" in the slow input transitions between solid logic 0 and logic 1.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Yep, messed up there. 10nS, but the theory is still valid, as I need 500nS of delay:

http://www.zimmers.net/anonftp/pub/cbm/ ... 6525-7.gif (see CB and CA notes in top left corner of page)

I figured I'd need to empirically test the delay to get it right...

I will have some extra pins on a 95144-100 to create the one shot, and I like it better as an idea. I assume you drive the output high, and then the input going high is your delay...

The trouble with propagation delay is, it's not predictable or well specified. No minimum figure, as Garth said.

A better way -- and the normal and natural way -- to implement a delay with programmable logic is via a counter. At the start of the delay the counter would be loaded, then it would proceed to decrement (or increment) according to a clock signal that's been chosen as a time base. The delay is complete when the counter reaches its terminal value (typically zero if you're decrementing).

That same basic idea can work for you, too. Presumably this 6526 device -- a 65xx peripheral -- gets the Phase 2 signal fed to it, and that can serve as your time base. From the datasheet you posted, I see the delay commences with a write to PRB. This would load your counter, which would subsequently decrement at the Phase 2 rate until the delay is complete. You'd arrange for CB to be low anytime the counter is not at its terminal value. This gives a nicely defined pulse following a write to PRB.

You'd need to decide whether the counter decrements on the rising or falling edge of Phase 2, and what the initial count should be. Looks like that count might be be extremely small -- like, 1! A simple flipflop might serve as the "counter." It would "count" from 1 down to zero. Possibly the original 6526 logic is just as I describe.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

For an uncalibrated delay, you could make an on-chip ring oscillator with an odd number of inverters - perhaps 5 or 7 - and use that fast signal to clock a counter. You could trim that by bringing one of the outputs off-chip and loading it with a capacitor, probably.