Correct.

I'm on spring break this week, so I have a bit more leeway to work on other things...

Let's see how much I can get accomplished before the break ends. I don't expect to be completely done obviously, but something minimal component and usable would be nice.

https://github.com/cr1901/65xx_DMA/tree/master

A problem I just realized while sketching the datapath...

If an I/O-to-mem xfer will happen in one bus cycle, it's important that the current address register be incremented each clock cycle. During a DMA cycle, the memory address will be prepared internally and clocked so that it appears on the external address bus on the positive edge of PHI2... by the negative edge of the next PHI2, the address needs to remain on the bus while the hold time for the data xfer is satisfied and propogation delays take effect inside the chip... But the negative edge of PHI2 is the point at which the address register needs to be incremented (clocked) in preparation for the next xfer! As soon as the hold time is satisfied, the controller tristates until it 'knows' that another free cycle is present.

Will the propagation delays (and clock-to-Q) internally be enough for the new address to be clocked in, without the address register accidentally placing the new value on the bus before a free cycle?

Also, another update-

I finally, more-or-less, fully understand how the 8237 controller works. There are at least parts of that design I feel I should use as a basis (current/base address register, current/base word count) to make my life easier. Against BDD's wishes . I should call it the 6537...