I'm not entirely sure if it is, although I have tried both a Rockwell R65C02P2 and a W65C22S-14 and both have the issue.
I could try putting the clock through a couple of inverters to slow it down (for the VIA only, of course). Do you think that would be enough to slow it? If not, what methods would you normally recommend?

Putting the clock through a schmitt inverter a couple of times didn't work.
I've got a few NMOS compatible versions of the 65c22 so I'll try one of those next.

[edit] Nope that didn't work either.

Did you try Garth's suggesting of attempting to read some value from the port? You just need to tie a couple of port pins high and some low.

I really would like to see this resolved and things working.

From what you've described, the connections are fine, and the code is fine.

So next, how's the construction? For several reasons, using solderless breadboards generally constitutes asking for trouble with fast parts, even if you run them at slow clock rates, because their fast rise times, couled with the inductance of the long hoops of wire, causes severe ringing and also way too much coupling between lines. This is mentioned in the Techniques for reliable high-speed digital circuits sticky topic and in the brief article in the 6502 primer on avoiding AC-performance problems. The first time I breadboarded a 65c02 computer, it was on a solderless breadboard, and it worked; but that was with 2MHz parts, so I got lucky even though I didn't realize the problems that can go with it yet. I do use solderless (plug-in) breadboards for audio and other low-speed applications, but wire-wrap works much better for this computer application for several reasons.

Short of just starting over though, the most important lines to cleean up is the clock distribution, even if you're single-cycling with a pushbutton. It might do wonders if all you do is use a twisted pair of wires for the phase 2 connections, with the second wire going to the grounds of the ICs at each end; for example, if U1 outputs the clock signal and U2 is one of the 65-family devices that uses phase 2, have the two wires of one end of the twisted pair go directly to U1's clock output and U1's ground, and, at the other end, have them go directly to U2's clock input and ground. Have as little untwisting at the ends as feasible. Use another twisted pair to go from the clock driver to each IC that needs it; ie, don't daisy-chain them.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thanks guys

I've tried reading outputs as suggested (using 3.3K resistors to ground for logic 0 and the same for to VCC for logic 1). I put in a pattern for $AA (10101010) and it gave me 0 (00000000) when read.

Regarding the breadboard: I'd heard that this might cause an issue, but wanted to explore all other avenues first (so will try your twisted pair idea when I get home). If that doesn't work then I might set up another 6502 on a second breadboard and construct just the bare basic, keeping the wire lengths as short s possible (I've just received more in the post).

Unfortunately, although I can try and construct this into a Veroboard, I don't have any wirewrap tools (they seem to be very expensive! ) I will need to solder it all (using DIL sockets).

Hmm - if you remove the VIA, do you get exactly the same? Can you show the relative timings of the chip select, register select and clock? I wonder if your problem is something obvious, and to find it you just have to revisit everything you think you know until it jumps out at you.

Cheers
Ed

You know, Ed might be on to something with this. With the VIA out of the socket, a read of it should return random values, since the data bus will be in an undriven and therefore undefined state during the read operation. If you get what appears to be a stable bit pattern on each read then you may have a bus contention problem or an electrical fault that is impressing voltage and/or ground where it should not be. The answer is probably obvious as Ed suggests.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

The sockets are kind of expensive but not astronomical unless you use the PLCC WW sockets. Just get the tin-plated ones, not gold, and skip the expensive screw-machine type. I have never had trouble with any of the inexpensive sockets I've used over the last 25 years. I just checked Mouser and Digi-key for the WSU-30M tool I recommended in the primer, and I was a bit surprised that they wanted $31. I got mine many years ago but I'm sure I didn't pay nearly that much. Whatever I paid, I figured it would be an investment that I would be using for many years. As for wire, they wanted 6.3 cents a foot for a thousand feet ($63 for 1000') or 12.3 cents a foot for a hundred feet ($12+ for 100'), and it's nice to have a roll of each of several colors.

And yes, problems usually hide in plain sight.


At normal operating speeds, if there are only CMOS loads on it, it will probably just return whatever value was driven on it last, like the last operand byte of the instruction, held there by bus capacitance. At pushbutton single-cycling speeds all bets are off though.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Well, I did a check to see what the chip selects of the EEPROM and the RAM are when the VIA is being written to and that shows that neither is selected and the VIA is selected. The R/W line is also low (selected). So unless something else(?) could cause bus contention then I don't think it's that. Time to try the twisted pair thing.

Regarding the wire wrap tool: Cheapest I can find from the UK is approx £33. ($55 approx). I'll have to have a think on the costs etc. and have a look at some videos on how to use one.

[edit] Would this one do?
http://www.ebay.co.uk/itm/OK-INDUSTRIES-WSU30M-WIRE-WRAP-TOOL-/350958386403?pt=LH_DefaultDomain_3&hash=item51b6bffce3

I've ordered the wire wrapping tool anyway. Nothing like learning something new... on top of something new!

[edit] The twisted pair idea didn't pan out, unfortunately. Looks like I'll have to build the project and see how it goes.

[apologies for anyone who read this earlier and now it's changed: the more I looked into this the more I learned/discovered the more I updated the post - sorry for any confusion]

I think I might have figured out the problem with the VIA not working:
Going by the decoding that currently exists in my project (see attached image), wouldn't the RAM and VIA enable at the same time?
Decoding process:

For /ROM select
Required address bus pattern: 1xxx xxxx
IC6C receives logic 1 from A15 and logic 1 from +5V rail
Active range: $8000-$FFFF

For /VIA select
Required address bus pattern: 0xxx xxxx
IC6B receives logic 1 from A14 and logic 1 from IC6C if A15 is logic 0
Using A0-A3 for RES0-RES3
Active range: $4000-$400F

For /RAM select
Required address bus pattern: 0xxx xxxx
IC6A receives logic 1 from CLK (when high) and logic 1 from IC6C if A15 is logic 0
Active range: $0-$7FFF

Problem 1: Basically, the RAM will be enabled unless A15 is logic 1. This means that the RAM and VIA (and the ACIA that I was planning to put in) will be enabled below address $8000. The VIA address is at $4000... and so we have bus contention .
Now, the /OE of the RAM chip is hooked up to A14. This will prevent a read if the VIA get selected (using A14), but what about writes? I don't know quite enough about bus contention. Does it happen during writing as well? From what I understand at the moment it would.

Problem 2: Like a twit I thought that the beginning address for the VIA was $6000. It's not - it's $4000 (binary 0100 0000). It changed when I followed advice and used (faster) NAND gates instead of a 3-8 decoder .

Does everyone concur with the above?
If so then I just have to figure out some slightly more complicated decoding. If I can't figure out how to do it with gates then I'll use the (albeit slower) 3-8 decoder.

[edited to add extra info]

Ok, if I need to, I can put an OR gate in the RAM /CS line (/RAM select). One of the inputs will be the /RAM select and the other the /VIA select.

Here's the extra gate. Before I add it in I'll test the $4000 address first. Before I do that I need to put the project back together again...

You can write to as many things as you want to at once, if it simplifies your circuit. Since my address map has the I/O ICs' addresses mirrored a lot, I could do that, for example to set up multiple VIAs the same way at the same time. Contention is when two or more things each try to force an output value on the bus at the same time, and they don't agree as to what that ought to be, so they fight each other-- hence the name "contention."


The VIA is selected when bit 15 is low, bit 14 is high, and bit 13 is high, because CS1 (pin 24) is positive logic, unlike CS2\ (pin 23) which is negative logic; so it is selected with the high address byte being 0110 0000. The diagram in the primer is basically the same as we have flying in a thousand aircraft, except that the one in the aircraft scrambles address lines and scrambles data lines to memory to make a tight board layout easier. Also my workbench computer uses only a single quad NAND for all address decoding, with 32KB ROM, 16KB of RAM (using half a 32Kx8), 3 VIAs and 3 ACIAs.

If you lived locally, I'd sure like to look at it. There's something else wrong and it might just take a fresh pair of eyes to see it.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thanks for advising (and for the extra information regarding bus contention). Also, thanks for the sentiment regarding taking a look/fresh pair of eyes. I'd normally show it to some of my friends, family or work colleagues, but they all look slightly glassy eyed when I start mentioning electronics and my project (and seem to fight the urge to run away I think) lol.

I forgot about CS1 on the VIA (despite it staring me in the face) - I was spending too much time concentrating on the decoding area and making assumptions that most chip enable/selects have negative logic. Thanks for correcting me on that.

Looks like my "eurika!" moment has gone south